Why the last ten millimetres are the hardest

Every essay in this series has walked one step closer to the transistor. Part I stopped at the rack, where 800V DC arrives across a bus. Part II showed how silicon carbide and gallium nitride step that voltage down in the power shelf. Part III showed how the resulting heat is removed. Part IV mapped the copper that moves the current across the rack once it has been converted. This essay picks up where Part IV stopped: at the accelerator's package edge, where 48V (or, in the older generations, 12V) enters and has to become 0.8V at the transistor gate, without dropping more than a few millivolts across the interconnect between.

That last conversion is where the physics gets hard. The transistor supply voltage on a leading-edge accelerator has collapsed roughly threefold over the last decade, from about 1.5V on 28nm to about 0.65V on 3nm and 2nm. Compute density has moved the opposite way. A single H100 die draws around 700W. Blackwell B200 draws about 1,200W. Blackwell Ultra targets ~1,400W per NVIDIA's published data. Rubin is expected to push much higher; specific per-package figures have not been confirmed publicly. Taking 1,800W as an illustrative anchor, at 0.8V that implies approximately 2,250 amperes of core current for a representative 1.8kW Rubin-class acceleratorThat current has to flow through metal that is at most a few micrometres thick, through a package that is at most a few millimetres tall, and at a resistance low enough that the IR drop across the delivery network stays within a few tens of millivolts of the transistor's specified operating window. Miss it by 50mV and the accelerator throttles.

Two constraints dominate the design space. First, ohmic loss scales with the square of current, so doubling current at constant voltage quadruples the heat rejected by the power path itself. Every millivolt of IR drop matters. Second, the current has to be delivered everywhere on the die at once, not only at the die edge. A modern accelerator has thousands of independent power domains, each with its own voltage and current profile, each transitioning between states in nanoseconds. The delivery network has to hold voltage stable across all of them, at kilohertz-to-megahertz transient frequencies. Node scaling keeps tightening the constraint faster than the delivery network can adapt to it.

The voltage staircase

The complete voltage staircase for a modern AI rack, laid out end to end, is one of the most compressed engineering hierarchies in modern electronics. Each stage has its own converter topology, its own dominant vendor, its own regulatory context, and its own failure mode. This essay is about the last three or four stages on the right of that staircase, but the whole picture is worth showing at once.

Read the chart from left to right. The utility supplies medium-voltage AC in the tens of kilovolts. The datacenter's power hall converts that to 415V or 480V three-phase AC, then increasingly to 800V DC at the rack. A silicon-carbide shelf steps 800V DC down to 48V DC at the board. A multi-phase point-of-load converter steps 48V to 0.8V at the accelerator. And an on-die power grid distributes that 0.8V across the transistor plane. The current at each stage is the mirror image: single amperes at the top, hundreds at the board, thousands at the die.

The essays in this series have covered the left half of that staircase in depth. This one covers the right half, from 48V downward.

Where the vendors sit: the on-package power map

The map below is the industry as it looks in mid-2026, with the qualification-gated bottlenecks marked. It is denser than the maps in earlier parts of the series because on-package power delivery has more distinct layers, each with its own vendor concentration and its own margin structure. Nothing about the map is stable on a three-year view. All of the foundry-level layers are moving.

L1. L2: The board-level converters and where their margins live

Before the substrate, before the interposer, before any of the foundry-level engineering, the accelerator gets its power from a set of discrete converter chips on the motherboard or the intermediate power module. These are conventional silicon parts, made on mature CMOS nodes, and sold as merchant devices. They are also where the visible profit pools of the on-package power stack currently sit.

The board-level path splits into two topologies. The older topology takes 48V from the rack bus, converts it to 12V through an intermediate bus converter (IBC), then converts 12V to the accelerator's core voltage through a multi-phase point-of-loadThe newer topology, pushed by hyperscalers to reduce conversion losses, converts 48V directly to core voltage in a single multi-phase stage, skipping the 12V intermediate. Direct 48V conversion is thermally and electrically harder but eliminates the roughly 3% loss of the IBC stage and removes a component category from the board.

Both topologies converge on the same critical layer: the multi-phase point-of-load. This is where the interesting economics sit. A modern accelerator's core voltage rail draws over a kilowatt at under one volt, which requires eight to twenty parallel converter phases operating in interleaved fashion to spread the current across enough physical devices to keep each below its thermal limit. Each phase is a "DrMOS" module (driver plus MOSFETs plus a control interface). The controller die orchestrates the phases, balances current between them, and manages transient response. Both the controller and the DrMOS parts are qualification-gated into the accelerator's reference design.

Monolithic Power Systems currently holds the strongest disclosed merchant position in AI-accelerator multi-phase POL. Its MP288x family holds design-in slots on Hopper, Blackwell and Rubin. Whether that makes MPS the durable reference vendor is a thesis, not a settled fact. The AI-server slice of MPS revenue is estimated at roughly $900M in 2025 growing to $1.4-1.6B in 2026 at operating margins that its filings suggest are the highest in the multi-phase space, in the 32-36% range. Empower Semiconductor is smaller (est. $180-220M in 2025) but grew fastest, because its hybrid IVR/DrMOS parts are the merchant substitute for Intel's captive FIVR. Analog Devices, Infineon and Renesas hold positions on non-accelerator power (server CPU, networking silicon, memory) and are contesting the AI accelerator slot with newer parts. Renesas' acquisition of Dialog gave it the digital-controller IP it lacked, and Infineon's OptiMOS DrMOS is the volume alternative to MPS. Texas Instruments participates but sits outside reference part placement on the leading accelerators.

The Chinese position at this layer holds but qualitatively different. Silergy and Kinetic Technologies have credible multi-phase parts and hold volume slots on Chinese hyperscaler accelerators (Huawei Ascend, Cambricon MLU, Enflame). They do not hold slots on NVIDIA or AMD reference designs, and there is no visible path to them doing so on the current-generation parts. The qualification cycle for a new controller in a hyperscaler AI reference design is 18-24 months and includes a full thermal, transient and electromagnetic co-simulation; that gate has held since Blackwell and shows no sign of loosening on Rubin.

L3: Integrated voltage regulators, and why Intel had this ten years early

The next step is to move the multi-phase converter from the board to the package itself. This is what an Integrated Voltage Regulator (IVR) is: the entire buck converter, including its magnetic inductor and its power switches, integrated into the substrate directly beneath the accelerator die. It shortens the current loop from centimetres to millimetres, cuts IR drop, and lets the converter operate at higher switching frequencies (tens of megahertz instead of hundreds of kilohertz), which shrinks the required inductor and capacitor values by roughly two orders of magnitude.

Intel introduced IVR technology, branded FIVR, on Haswell in 2013. The engineering was ahead of its time, and Intel wound the technology down on Skylake for reasons that were as much strategic as technical: FIVR needed high-current-density magnetics that were expensive to fabricate, and moving voltage regulation off the motherboard shifted the industry BOM in ways that Intel's OEM customers pushed back on. The technology never disappeared. Intel reintroduced elements of it on Meteor Lake, and it now returns as a core requirement on Rubin-class accelerators, this time from the merchant vendor side.

The merchant IVR vendors are Empower Semiconductor, Ferric Semiconductor (acquired by TDK in 2025), and, at lower volumes, several Japanese magnetics houses (TDK, Murata) supplying the thin-film magnetic components that make IVR economically viable. Empower's thin-film inductor process, developed in partnership with Intel over the preceding decade, is the closest thing to a merchant equivalent of FIVR. Ferric's technology, now inside TDK, is the alternative. Both companies solved the same problem: fabricating magnetic cores with high enough current density to sit in a package substrate, in a footprint measured in single-digit square millimetres, at frequencies above 20MHz. The manufacturing capital intensity is substantial. Neither company faces material Chinese merchant competition at the AI-accelerator-qualified integrated voltage regulator layer as of mid-2026. Chinese domestic AI vendors qualify Chinese POL suppliers (Silergy, Kinetic) at the discrete multi-phase POL layer but not at IVR.

The strategic question about IVR concerns whether the merchant IVR value migrates upward into the foundry, downward into board-level multi-phase, or holds its ground as a separately merchant layer. That IVR itself works has been settled for years. The current answer is a hedged one: on the flagship accelerators of 2026-2027, IVR is on the package as a merchant component from Empower or TDK, sharing the substrate with the accelerator die. On the 2028+ generation, the migration path is upward: TSMC and Intel are both engineering power regulation into the interposer itself, using the same thin-film magnetics techniques but delivered as part of the packaging service. If that migration completes, Empower's addressable market compresses onto second-tier accelerators and Chinese domestic AI silicon.

L4. L5: Vertical Power Delivery and Backside Power Delivery, the foundry-level architectural shift

Everything below this section is happening inside the foundry, at the level of the semiconductor process itself. It is where the on-package power stack transitions from a business of buying and stacking merchant components to a business of choosing an architectural path for the whole accelerator.

To understand what has changed, think about how power reached the transistor on a 7nm or 5nm accelerator. The die had ten to fifteen metal layers stacked on top of the transistor plane. Signal routing and power distribution shared those metal layers. Power came in through solder bumps around the die's perimeter, threaded through the substrate up into the front side of the die, then travelled downward through the metal stack to reach the transistors. Signal routing took the same path in reverse. As dies scaled, this shared-metal-stack model started to run out of room: the transistors were getting smaller but the power grid needed thicker, wider metal to transmit the current, and the two demands fought each other for area on the same metal layers.

Backside Power Delivery Networks (BSPDN) solve the fight by moving power to a separate metal stack on the back of the die. The transistor plane is in the middle, signal routing is on the front-side metal stack, and power routing is on the back-side metal stack. The two never share area. Because the back-side power stack does not need to leave room for signals, its metal can be much thicker and wider, moving more current with less IR drop. And because the transistors receive power from behind, with top-side power delivery deprecated, the power path from the substrate to the transistor gate is measured in single-digit micrometres (down from tens of micrometres), cutting resistance by more than half.

The three foundries take slightly different paths. Intel's PowerVia is in volume on the 18A node from H2-2025, ahead of the pack by roughly nine to twelve months. TSMC's SuperPower Rail enters volume with N2P in H2-2026 and expands to A16 in 2027. Samsung Foundry's BSPDN is targeted for SF2P in 2027-2028. All three implementations achieve the same first-order goal: they reduce IR drop by 30-50% versus the front-side-only equivalent, unlock roughly 5-10% higher clock frequency at the same power, and roughly 5-8% lower power at the same clock. The differences are in yield ramp curves, in the specifics of how the back-side stack is fabricated (wafer thinning, temporary carrier bonding, direct wafer-to-wafer hybrid bonding for the highest-performance implementations), and in the manufacturing equipment supplied by Applied Materials, Lam Research, ASML and Tokyo Electron.

Vertical Power Delivery (VPD) is the packaging-level counterpart. Where BSPDN routes power on the die's back-side, VPD routes power through the substrate to the die's back-side. VPD without BSPDN is possible (the current can still be routed through the die from back to front on a conventional front-side power grid) and is used on hyperscaler accelerators that have not yet moved to a BSPDN foundry node. The full stack is VPD + BSPDN, and Rubin's most power-hungry configurations are the first commercial parts to run both together.

The commercial implication of BSPDN is straightforward: on any leading-edge accelerator manufactured from 2026 onward, the choice of foundry is the choice of power architecture. There is no third-party BSPDN vendor. There cannot be, because the technology is inseparable from the front-end wafer process. That is why hyperscaler chip programs (Google TPU, AWS Trainium, Microsoft Maia, Meta MTIA) are structurally tied to their foundry partners: switching foundries midway through a program means redesigning the entire power distribution network.

L6: Silicon interposers, the layer above the die

Between the accelerator die and its substrate lands the interposer. On a leading-edge AI part, this is a piece of silicon (or, increasingly, glass) that holds the interconnect between the accelerator's compute die, its high-bandwidth memory stacks, and its off-package connections. The interposer is the physical structure that makes 2.5D and 3D packaging possible, and its power delivery role is often overlooked.

Every through-silicon via (TSV) on the interposer is a candidate power via. Modern accelerator interposers hold thousands of TSVs, and a substantial fraction of them are dedicated to power delivery; signal routing takes the remainder. The interposer is what physically routes the power from the substrate up into the die's back-side (on VPD) or around the die into the front-side power grid (on conventional designs). Interposer resistance and inductance therefore sit directly in the IR drop budget.

TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is the volume interposer for merchant AI silicon. It comes in three flavours: CoWoS-S (silicon interposer, the original), CoWoS-L (with a local silicon interconnect bridge, cheaper for smaller dies), and CoWoS-R (RDL redistribution layer without a full silicon interposer, cheapest but with lower TSV density). NVIDIA Hopper, Blackwell and Rubin all use CoWoS variants. Capacity is famously tight: TSMC's public disclosures put 2026 CoWoS capacity at roughly 75,000 wafers per month, up from 45,000 in 2025 and 15,000 in 2023, and every incremental wafer is spoken for eighteen months in advance.

Intel's Foveros is the alternative on Intel-manufactured parts, with its own set of packaging variants (Foveros Direct for hybrid bonding, Foveros Omni for redistribution). Samsung's X-Cube holds a smaller position, largely inside Samsung's captive silicon. ASE's VIPack, Amkor's SLIM and JCET's XDFOI are the OSAT (outsourced assembly and test) alternatives, playing at lower TSV densities and lower current requirements than the flagship AI parts but growing fast on the second-tier accelerator market.

L7: Glass substrates, the disruptive layer

The substrate is the piece of packaged organic material that is senior to the interposer and provides the electrical connection to the motherboard. The incumbent technology is organic laminate (typically ABF, Ajinomoto Build-up Film, a Japanese resin), pressed into build-up layers with copper traces etched between them. The Japanese substrate industry (Ibiden, Shinko, Kyocera) has led this technology for two decades. The Korean and Taiwanese entrants (LG Innotek, Simmtech, Nan Ya, Unimicron) have closed most of the gap on volume but not on the highest layer counts.

The problem with organic laminate is that it warps. As accelerator dies get larger (Blackwell's compute die is 814mm², two dies bonded, Rubin larger still), the substrate has to hold that die flat within tens of micrometres across roughly 100 × 100 mm of substrate area. Organic laminate's coefficient of thermal expansion (CTE) does not match silicon's, so as the package heats and cools, the substrate warps against the die. On smaller packages this is manageable. On the physically largest packages in the industry, it becomes a yield problem.

Glass substrates solve this by replacing the organic build-up layers with glass. Glass has a CTE much closer to silicon's, is more rigid, and can support higher via densities. Intel announced its glass substrate roadmap in September 2023 with volume targeted for 2026-2027. Absolics, a subsidiary of Korea's SKC, began commercial shipments of glass substrates from its Covington, Georgia facility in H2-2025. Corning, LG Innotek, Samsung Electro-Mechanics and Dai Nippon Printing are all in the market. AGC and Nippon Electric Glass supply the underlying glass sheets.

Two structural points about the glass substrate layer matter for the profit-pool question. First, the technology gap between Korean and Japanese substrate incumbents is much smaller in glass than in organic laminate. Absolics is genuinely competitive with Intel's captive glass on a first-generation basis, which does not happen often in packaging. Second, the Chinese position is absent. Shennan Circuits and other Chinese substrate manufacturers are established at the low-end organic laminate level but have no visible glass substrate program at datacenter grade. The gap here mirrors the BSPDN gap: the tools, the process knowledge and the customer relationships that would allow rapid Chinese entry are all missing.

L8. L9: The incumbent substrate layer and the on-die metal stack

Layer 8 is the organic substrate business that glass is displacing from above. It is a large business (roughly $12-14B in 2025, growing single-digits) and it will remain the volume solution for accelerators below the flagship tier for years. The Japanese majors (Ibiden, Shinko, Kyocera) hold the highest layer counts. Korean entrants (LG Innotek, Simmtech) hold the mid-tier. Taiwanese and Chinese vendors dominate the low-tier. The interesting margin story is what happens as glass takes share off the top: Ibiden and Shinko lose the highest-priced product line first, and the volume that remains at organic laminate is progressively lower-margin. This is a sustained profit pool compression at the incumbent, over the 2026-2030 window.

Layer 9, the on-die metal stack, is a foundry-integrated business. Nothing about it is separately merchant. It belongs in the map because the equipment suppliers (Applied Materials for deposition, Lam Research for etch, Tokyo Electron for coat/develop, ASML for lithography) capture a material share of the value that flows through this layer, and their AI-driven revenue lines run through here. The specific innovation at this layer that counts for the on-package power thesis is the introduction of ruthenium as an interconnect metal on the top-most power routing layers, which offers lower resistance than copper at the smallest line widths and is being introduced at 2nm and A16 nodes. This is the final segment of the delivery path: the current-conducting metal at the transistor gate itself.

Sizing the market and locating the profits

Bottom-up TAM

Build the market from AI IT-load additions, as in Parts I, II, III and IV. On-package power delivery content per rack: multi-phase controllers and DrMOS on the accelerator board average roughly $2,200 per 1,800W accelerator (up from $1,400 for a 700W H100). At 8 accelerators per NVL72-class rack tray, this is $17,600 per tray, and roughly $70,000 per NVL144 rack once the IBC and supporting components are included. Substrate, interposer and packaging content per rack: CoWoS-class packaging runs $2,500-4,000 per accelerator die at current TSMC pricing, so roughly $80,000-130,000 per NVL144 rack. BSPDN and on-die metal: embedded in the accelerator's wafer cost.

Combining the visible layers, on-package power delivery content is at roughly $450-650 per kW of AI IT load, plus a further $100-150/kW captured inside the accelerator wafer cost; separate merchant pricing stays absent. Multiplying against roughly 8GW of new AI IT-load added in 2026 gives a bottom-up TAM of $4.0-5.5B for the visible layers, plus another $0.8-1.2B captured inside foundry pricing but attributable to power delivery. Published market sizings for the broader "AI power management" category cluster around $7-10B for 2026, with 20-25% CAGRs. The reconciliation gives confidence in the $8-10B combined figure, understanding that some fraction of that is embedded in foundry wafer prices; separate quoting stays absent.

Where the profits sit

The layer-by-layer margin structure is more differentiated than in the earlier essays. The board-level layers (L1, L2) are high-margin at the AI-server slice (28-35% operating) and low-margin at the non-AI slice (12-18% operating), producing a mixed corporate margin at vendors like MPS that is nonetheless improving as AI mix rises. The IVR layer (L3) is a niche but with structurally high margins (35-45% at Empower, difficult to verify given its private status). The foundry-controlled layers (L4, L5, L6, L9) do not have separately-visible margins because they are captured inside foundry pricing; the effective margin is TSMC's or Intel Foundry's, which is at 40-55% gross on leading-edge nodes. The glass substrate layer (L7) is new and margin structure is early Absolics unit economics suggest gross margins in the 35-45% range on first-generation product, which will compress as competition builds.

Summary matrix: on-package power delivery vs the rest of the AI power chain

Reading the map for the next three years

Three moves are already visible in the 2026-2028 window, and each of them changes the merchant profit pool at a specific layer.

First, IVR consolidation upward into the foundry. Both TSMC and Intel are engineering thin-film magnetics into their interposer processes. If that consolidation completes on the Rubin+ generation, the merchant IVR market compresses onto second-tier accelerators, and Empower's addressable market shrinks by roughly one third. Watch for foundry announcements at IEDM 2026 and IEDM 2027.

Second, glass substrate share taking the top of the organic laminate market. On a five-year view, glass takes the flagship AI slot and the flagship server-CPU slot, leaving organic laminate to hold the mid-tier and mainstream server business. The Japanese incumbents lose their highest-margin product line first. Ibiden's substrate revenue mix will be the most watched line in Japanese electronics reporting through 2027.

Third, BSPDN broadening from Intel-first to a three-foundry norm. Intel PowerVia has an 12-18 month lead on TSMC SuperPower Rail today. That lead compresses as TSMC N2P ramps in H2-2026 and A16 in 2027. On the 2028 flagship node, all three foundries have BSPDN in volume, and the technology moves from "which foundry" to "which node within a foundry". The competitive question shifts from having BSPDN to how efficiently each foundry integrates it into their process, and how it interacts with hybrid bonding, glass substrates and thin-film magnetics.

All three of these moves reduce the merchant addressable market at a specific layer and expand the foundry captive market. The net effect over the 2026-2030 window is that value flows upward: from board-level multi-phase (L2) into IVR (L3), from IVR into interposer (L6), from organic substrate (L8) into glass (L7), and from front-side power distribution into BSPDN (L5). Every one of those flows narrows the field of merchant winners.

The cross-series thesis in one paragraph

This essay closes the arc that Part I opened. The AI power chain begins at the medium-voltage utility bus and ends at a 0.8V transistor gate drawing 2,250 amperes. Every essay in the series is a slice through that path. Part I sized the capacitor stack that stabilises 800V DC at the rack. Part II sized the wide-bandgap conversion that steps 800V down to 48V. Part III sized the thermal system that removes the heat released along the way. Part IV sized the interconnect that moves the current between conversion stages. This one sizes the last conversion, from 48V to 0.8V, and the physical structures inside the accelerator package that make it possible. Part VI will size the modular civil and electrical infrastructure that lets datacenter operators build the whole thing at industrial scale. Read together, the six essays add up to a single question: which layers of the AI power chain have defensible margins over the 2026-2030 window, and which layers become commodity as the volume ramps? On the evidence collected across this series, the answer is consistent: qualification-gated layers with high consequence of failure and small bill-of-materials percentages hold their margins; volume-metal-and-plastic layers do not. On-package power delivery has more of the former than any other essay in the series.