The AI Power Chain · Part V of VI

The On-Package Delivery Stack

The 10 millimetres of interconnect that carry 1,000 amperes into a 0.8-volt transistor plane, and the foundry-level architecture change now under way to make them scale.

The AI Power Chain · six essays, one thesis
  1. Part I. The Capacitor Stack: 800VDC at the rack
  2. Part II. The Wide-Bandgap Stack: SiC and GaN conversion
  3. Part III. The Thermal Stack: removing the waste heat
  4. Part IV. The Interconnect Stack: busbars and whips
  5. Part V. The On-Package Delivery Stack: 48V to 0.8V (you are here)
  6. Part VI. The Modular Datacenter Stack: how the building gets built

Executive summary

  • Public analysis of the AI power path usually stops at the rack. The layer below, from 48V down to 0.8V flowing through interconnect the width of a hair at 1,000 amperes, is where the current generation of accelerators is thermally and electrically limited, and where the next architectural shifts are happening.
  • Two changes are landing at once. Vertical Power Delivery (VPD) moves DC feed from around the die to through the die's back-side. Backside Power Delivery Networks (BSPDN) etch a dedicated metal power plane beneath the transistor layer, freeing the front-side stack for signal routing. Both are foundry-level architectural changes, not board-level ones.
  • TSMC's SuperPower Rail lands with N2P in H2-2026 and A16 in 2027. Intel PowerVia is in volume on the 18A node from H2-2025. Samsung Foundry follows on SF2P in 2027–2028. In parallel, glass core substrates from Intel, Absolics (SKC), Corning, LG Innotek and Samsung Electro-Mechanics enter datacenter packaging in the 2026–2028 window, driven by structural stiffness and current density more than by dielectric properties.
  • The vendor map splits cleanly. Discrete power stages and multi-phase controllers (Monolithic Power Systems, Infineon, Renesas, Analog Devices, Vicor, Empower Semiconductor, Alpha & Omega) sit above the substrate. On-die and on-package power (TSMC, Intel Foundry, Samsung Foundry, ASE, Amkor, Powertech) sits inside the package. The two do not compete directly. They stack.
  • Total addressable market for on-package power delivery is roughly $8–10B in 2026, growing 22–28% CAGR into the early 2030s. The highest-margin layers are qualification-gated: MPS and Empower for AI-grade multi-phase (28–35% operating margins on the accelerator-facing revenue line), IVR patents cross-licensed between Intel, AMD and Nvidia, and TSMC and Intel Foundry running de-facto monopolies on BSPDN for the first 18–24 months of each node.
  • The Chinese position is real at the discrete VRM layer (Silergy, SG Micro, Kinetic Technologies) and structurally absent at the BSPDN and glass-substrate layers. That gap is the widest anywhere in the AI power chain, and the tightest chokepoint in the series.
The AI Power Chain · six essays, one physical arc

The series walks a single physical path. It begins at the medium-voltage utility bus at the site fence, steps down through the substation and switchgear, arrives at the datacenter rack where 800V DC is stabilised by the capacitor stack, is converted by silicon-carbide switches to 48V, is distributed across the rack by copper busbars and whips, is stepped down again by multi-phase controllers on the accelerator board to 0.8V, and finally routed through the on-package power delivery network to a transistor gate drawing over 2,000 amperes. Waste heat from every conversion stage is removed by the thermal stack. The whole thing is packaged inside a factory-modular building because there aren't enough electricians to build it stick-frame. Six essays. One 800V → 0.8V staircase.

  1. Part I. The Capacitor Stack — 800VDC at the rack
  2. Part II. The Wide-Bandgap Stack — SiC and GaN conversion
  3. Part III. The Thermal Stack — removing the waste heat
  4. Part IV. The Interconnect Stack — busbars and whips
  5. Part V. The On-Package Delivery Stack — 48V to 0.8V (you are here)
  6. Part VI. The Modular Datacenter Stack — how the building gets built

Why the last ten millimetres are the hardest

Every essay in this series has walked one step closer to the transistor. Part I stopped at the rack, where 800V DC arrives across a bus. Part II showed how silicon carbide and gallium nitride step that voltage down in the power shelf. Part III showed how the resulting heat is removed. Part IV mapped the copper that carries the current across the rack once it has been converted. This essay picks up where Part IV stopped: at the accelerator's package edge, where 48V (or, in the older generations, 12V) enters and has to become 0.8V at the transistor gate, without dropping more than a few millivolts across the interconnect between.

That last conversion is where the physics gets hard. The transistor supply voltage on a leading-edge accelerator has collapsed roughly threefold over the last decade, from about 1.5V on 28nm to about 0.65V on 3nm and 2nm. Compute density has moved the opposite way. A single H100 die draws around 700W. Blackwell B200 draws about 1,200W. Rubin is targeting 1,800–2,000W. At 0.8V, 1,800W is 2,250 amperes. That current has to flow through metal that is at most a few micrometres thick, through a package that is at most a few millimetres tall, and at a resistance low enough that the IR drop across the delivery network stays within a few tens of millivolts of the transistor's specified operating window. Miss it by 50mV and the accelerator throttles.

Two constraints dominate the design space. First, ohmic loss scales with the square of current, so doubling current at constant voltage quadruples the heat rejected by the power path itself. Every millivolt of IR drop matters. Second, the current has to be delivered everywhere on the die at once, not just at the die edge. A modern accelerator has thousands of independent power domains, each with its own voltage and current profile, each transitioning between states in nanoseconds. The delivery network has to hold voltage stable across all of them, at kilohertz-to-megahertz transient frequencies. Node scaling keeps tightening the constraint faster than the delivery network can adapt to it.

A single Rubin-generation accelerator will draw approximately 2,250 amperes at 0.8 volts. That current has to flow through metal a few micrometres thick, at an IR budget of a few tens of millivolts, or the transistor throttles.The design constraint

The voltage staircase

The complete voltage staircase for a modern AI rack, laid out end to end, is one of the most compressed engineering hierarchies in modern electronics. Each stage has its own converter topology, its own dominant vendor, its own regulatory context, and its own failure mode. This essay is about the last three or four stages on the right of that staircase, but the whole picture is worth showing at once.

The AI voltage staircase: rack to transistor
Voltage and current at each conversion node, hyperscale AI rack, log-scale current axis
Author's construction from published NVIDIA / Vera Rubin platform disclosures, hyperscaler design notes and vendor product documentation. Voltages are nominal; currents are approximate for a 210kW rack-class system with a single 1,800W accelerator at the bottom of the chain. Current axis is logarithmic. Each conversion node has efficiency losses not shown here (see Annex §A1).

Read the chart from left to right. The utility supplies medium-voltage AC in the tens of kilovolts. The datacenter's power hall converts that to 415V or 480V three-phase AC, then increasingly to 800V DC at the rack. A silicon-carbide shelf steps 800V DC down to 48V DC at the board. A multi-phase point-of-load converter steps 48V to 0.8V at the accelerator. And an on-die power grid distributes that 0.8V across the transistor plane. The current at each stage is the mirror image: single amperes at the top, hundreds at the board, thousands at the die.

The essays in this series have covered the left half of that staircase in depth. This one covers the right half, from 48V downward.