The wafer layer: chokepoint to commodity

Silicon carbide sublimes (it does not melt), and that is the constraint the whole industry works around. You cannot pull a SiC boule the way you pull silicon from a Czochralski melt; you grow it by physical vapour transport, sublimating powder at ~2,300°C and re-condensing it on a seed crystal at millimetres per hour. A silicon boule grows in a couple of days and is two metres long. A SiC boule takes a week or more and yields perhaps 25-35mm of usable crystal. Then you cut it, with a material harder than almost anything except diamond, which is why wire-saw kerf loss historically destroyed a third of the crystal and why laser-based "cold split" techniques (Infineon's Siltectra acquisition) are strategically significant.

Substrates held 40-50%+ of device cost for a decade, and every serious SiC device maker locked in captive supply during that era: onsemi acquired GT Advanced Technologies in 2016, ST bought Norstel in 2019, ROHM has run SiCrystal in-house since 2009, and Coherent inherited II-VI's franchise from the 2022 merger. Chinese capacity then arrived at scale. Beijing named SiC a strategic material, a reported CNY 50bn (~$7bn) national fund flowed across 2024-25, and Chinese substrate output ran from ~460k units in 2022 through 2.22M in 2024 to an estimated 3.9M in 2025, projected toward 7.7M by 2027.

Market structure and share

Wolfspeed still led the substrate market with roughly 34% share in 2024, but the composition beneath it tells the story. TanKeBlue and SICC hold ~17% each, having arrived from effectively nowhere, with Coherent at ~14%. The top five (adding SiCrystal/ROHM, Resonac, SK Siltron) control about half of global capacity. SICC leads Chinese 8-inch. TanKeBlue is the volume domestic supplier. Meanwhile Japanese and Korean suppliers (Resonac, Sumitomo Electric, SK Siltron CSS) position explicitly as the non-Chinese alternative for Western automakers and, increasingly, for data center supply chains where provenance rules bite.

The 200mm (and now 300mm) transition

The economics are unambiguous. Moving from 150mm to 200mm yields roughly 2.2x more die per substrate and up to ~40% lower cost per die, with wafer-level cost roughly 35% lower. Everyone is going there: Wolfspeed's Mohawk Valley (the first 200mm SiC fab, backed by CHIPS Act funding), Infineon's Kulim Module 3 in Malaysia now ramping, ST's Catania campus, and onsemi's Czech expansion supported by a ~€530M EU state aid package. The catch is that 200mm yields have lagged. Industry commentary through 2025 put average yields below 50%. That compressed margins for everyone at the same time, because you book the depreciation of the new fab while still selling the old wafer's economics.

Then, in January 2026, Wolfspeed reportedly demonstrated a 300mm SiC bouleThis claim rests on a single research-house reference and has not been corroborated by Wolfspeed primary disclosure at time of writing; treat it as reported (confirmed status stays absent). If real, that positions Wolfspeed for standard-setting; near-term volume stays a different story. Whoever defines the format that customers validate gets to drive a decade of tool roadmaps, and it is a reminder of what the restructuring preserved: the balance sheet failed, the materials science did not. One further caveat: a boule demonstration is many years from qualified 300mm production.

Epitaxy: where substrate quality becomes device economics

Between the polished substrate and the device lies the epitaxial layer, the doped, defect-controlled crystal film the device runs on. Epi determines blocking voltage and determines yield. A basal-plane dislocation propagating from substrate into epi will kill a MOSFET's reliability under bipolar stress. Epi is the step where substrate quality either converts into device economics or doesn't. It is also why the substrate price collapse has not fully passed through to device prices: good epi on cheap substrate is still not cheap.

Most volume epi is captive (Wolfspeed, Infineon, ST, onsemi, ROHM all run their own), which keeps the merchant market small but strategically visible. Resonac is the leading merchant epi-wafer supplier, Wolfspeed offers 200mm epi commercially, and Chinese players (Epiworld, Enkris for GaN) have scaled fast.

The layer punches above its revenue for a few reasons.

Epi is where the substrate glut gets taken up or wasted. A cheap substrate with high basal-plane dislocation density still produces expensive devices because the yield loss shows up downstream. That mechanism is why the price war has hurt Chinese device makers less than expected and Western ones more: the incumbents were already buying good material and had less to gain from cheap wafers.

Reactor throughput is the hidden cost driver. SiC epi grows at a few microns per minute, and a 1200V device needs 10-12µm of drift layer, so reactor time per wafer is measured in tens of minutes against seconds for many silicon steps. Wafers per hour per tool is a first-order determinant of fab economics, which is why the tool choice matters as much as the recipe.

The equipment layer itself is a genuine oligopoly. Aixtron and Italy's LPE dominate SiC epi reactors, with Veeco and Japanese suppliers in adjacent positions. That makes it one of the cleanest ways to hold exposure to WBG volume without picking a device winner. The tools get bought whether the wafers end up in a Chinese fab or a German one.

For GaN the picture inverts. GaN-on-silicon epi runs on MOCVD tools (Aixtron and Veeco again, plus Chinese suppliers) on 200mm silicon substrates, and the epi is the hard part because you are growing a lattice-mismatched film on a foreign substrate. GaN's cost curve therefore behaves like silicon's while its supply chain behaves like a compound semiconductor's. That is why foundry partnerships (Navitas / PowerChip, Navitas / GlobalFoundries, Innoscience's integrated epi) determine competitive position more than in SiC.

Who are the five vendors that dominate SiC power devices?

Roughly five companies (STMicroelectronics, onsemi, Infineon, Wolfspeed, ROHM) have controlled 90%+ of SiC device revenue. ST has led on the strength of automotive MOSFETs (the Tesla relationship being the origin story of the modern SiC industry) and is completing its vertically-integrated Catania campus plus the Sanan joint venture in China. onsemi rose fast on EliteSiC with >50% substrate self-sufficiency post-GTAT, added Qorvo's SiC JFET business for $115M in January 2025, and secured EU state aid for Czech capacity. Infineon has the broadest portfolio across Si, SiC and GaN, launched trench-based SiC superjunction devices claiming ~40% lower R_DS(on)×A, and has stated a "30-30" goal of 30% global SiC share by 2030.

What AI changes is the voltage and mission profileAutomotive SiC is a 750-1200V, cost-obsessed, AEC-qualified game. Data center SiC spans a wider range: 1200V for the sidecar/rectification stages, and increasingly the 2300V and 3300V classes for medium-voltage grid interface and solid-state transformer work, where Navitas' GeneSiC trench-assisted planar devices have carved out a genuine niche against much larger firms. Japanese module houses (Mitsubishi Electric, Fuji Electric, Toshiba) hold the traction and industrial-drive strongholds and are natural beneficiaries of any MV-DC build-out. Bosch is the automotive-captive wildcard.

Chinese domestic substitution is moving up-stack

The market essay's story about Chinese wafer capacity is well-worn; what is less discussed is that Chinese players are now moving up the value chain into qualified device production for domestic hyperscale. BYD Semiconductor, United Nova (UNT), BASiC Semiconductor and AccoPower are all shipping SiC MOSFETs into Chinese EV programmes and, increasingly, into Chinese cloud infrastructure (Alibaba, Baidu, Tencent, ByteDance). Chinese hyperscalers have their own strong provenance preferences that cut the opposite direction to Western ones. The practical implication for the TAM discussed later in this piece is that the $9-14B 2030 base case is a global figure; the Western-hyperscale addressable slice is materially smaller, because Chinese cloud demand will largely be served by Chinese devices as their qualification cycles complete through 2027-29. The annex includes a Western vs Chinese TAM split as a stress test.

Where does GaN fit in AI data centre power?

Gallium nitride plays complement to SiC more than competitor, and the division is physical. SiC handles high voltage and high power with superior thermal conductivity: grid-to-rack conversion, traction inverters, MV interfaces. GaN switches faster at moderate voltages, which means smaller magnetics, higher power density, and better efficiency in the intermediate and point-of-load stages inside the rack. Gartner's framing of Infineon's advantage captures the consensus precisely: SiC for high-efficiency, high-voltage grid-to-rack conversion; GaN for ultra-dense, high-frequency intermediate stages; silicon at the processor level.

The competitive structure is younger and stranger than SiC's. Innoscience (China) leads with roughly 30% share, vertically integrated down to epi wafers, with an 8-inch GaN-on-Si platform and a partnership with ST that gives it Western reach. Infineon bought GaN Systems for $830M per company press release (announced March 2023, closed October 2023), still the largest transaction in the category, and is developing 12-inch GaN-on-Si pilot lines. Renesas acquired Transphorm for $339M and is on track to surpass $100M in GaN revenue. Power Integrations has PowiGaN plus the Odyssey vertical-GaN asset. EPC remains the low-voltage e-mode pioneer. Navitas has executed the sharpest strategic pivot in the sector, moving out of consumer chargers into "Navitas 2.0", with high-power markets contributing a majority of revenue for the first time in Q4 2025, a GlobalFoundries partnership for US-based GaN manufacturing, and 200mm GaN-on-Si at PowerChip for its 100V FETs.

Innoscience has integrated back into gallium supply itself, which turns the raw-material risk flagged elsewhere in this piece into a company-specific advantage. It listed on the HKEX in December 2024, raising roughly $180M and giving the GaN category its first Chinese-domiciled listed vehicle. The 2025 co-development agreement with STMicroelectronics gives it a Western-qualified path into designs that provenance rules would otherwise close. The 8-inch GaN-on-Si platform (competitors sit at 6-inch or pilot 12-inch), plus vertical integration from epi through devices, adds up to a per-die cost structure the rest of the field is chasing on the 100-650V parts that dominate rack-power and consumer sockets. Not an M&A target in any realistic scenario. National champion status makes its capacity trajectory a major exogenous variable in every non-Chinese GaN player's model.

Navitas' 800V-to-6V power delivery board, shown in the NVIDIA MGX ecosystem at Computex 2026, eliminates the traditional 48V intermediate bus converter stage inside the compute tray altogether. Removing a conversion stage from the architecture redistributes BOM dollars permanently, which is why this product matters more than a typical efficiency step.

GaN's substrate economics

GaN commercial architectures split three ways on substrate, and the cost curves diverge sharply. GaN-on-Si is the volume play: buffer layers manage the ~17% lattice mismatch to a silicon substrate, and the epi runs on depreciated 200mm (increasingly 300mm) silicon foundry lines. Substrate cost per wafer is essentially the silicon commodity price. The constraint has moved from the substrate to yield. This is the architecture Innoscience, Infineon (GaN Systems), EPC, Navitas and Power Integrations all use for <900V products. GaN-on-SiC uses a silicon carbide substrate for its superior thermal conductivity, and is the workhorse for RF GaN (Qorvo, Wolfspeed's RF business, MACOM). Substrate cost is roughly 5-10x GaN-on-Si, but the thermal-conductivity advantage matters where power density is extreme. Bulk GaN substrates (GaN-on-GaN) eliminate lattice mismatch entirely and enable vertical GaN devices, but production-scale GaN substrates remain rare and expensive; the market is measured in tens of thousands of wafers per year, mostly from Sumitomo Electric and Mitsubishi Chemical. Bulk GaN is the enabling substrate for the vertical GaN devices that could break the 650-900V ceiling of the lateral architecture, and its scale-up curve is a critical variable in the market essay's vertical-GaN thesis.

The near-term implication: GaN-on-Si dominates the <900V rack-power sockets because its cost curve tracks silicon; GaN-on-SiC holds specialty niches; GaN-on-GaN is the technology to watch for the 1200V+ vertical transition. Foundry yield curves matter for the first two more than substrate cost, because substrates are commoditised (Si) or affordable-if-specialised (SiC).

Two notes on the structure of this layer. First, foundries matter more in GaN than SiC because GaN-on-Si runs on depreciated silicon lines. TSMC's announced exit was a shock, but GlobalFoundries, PSMC, Vanguard, X-FAB and Polar have filled in, and Samsung is preparing a 2026 entry. Second, onsemi's absence is conspicuousYole's assessment that its entry is inevitable is the sort of thing that gets resolved by acquisition; organic development stays unlikely.

Where did the SiC scarcity migrate to?

Thin revenue, high torque. A materials-first reader should spend time here. A SiC die switching 1200V at high frequency generates heat in a smaller area than a silicon die and runs hotter. The package usually limits the module before the die does. The critical component is the ceramic substrate that carries the die, insulates it, and conducts its heat out: DBC (direct bonded copper) on alumina or aluminium nitride for conventional parts, and AMB (active metal brazed) silicon nitride for the demanding ones. Si₃N₄ now represents over 95% of the AMB mix because its fracture toughness survives the thermal cycling that cracks alumina.

This market is small in revenue but tight in supply. Estimates put it somewhere between ~$250M and ~$1.2B depending on scope, growing 9-30% depending on whose definition you take. The top eight suppliers estimated to hold ~80-90%Rogers (curamik) and Heraeus (~15% share) anchor the Western supply. Kyocera, Denka, Mitsubishi Materials, NGK/Niterra, Toshiba Materials, DOWA and Proterial give Japan extraordinary depth. Production splits roughly Japan 27%, Germany 25%, China 43%, with China projected toward 57% by 2030. Most Chinese lines remain in qualification, which is the same story as substrates one cycle earlier, and should be read the same way.

Two live dynamics stand out. First, silverSintered-silver die attach is what makes high-temperature SiC modules reliable, and it ties the industry's cost base to a volatile precious metal. Heraeus now markets a silver-free AMB substrate explicitly as a hedge against precious-metal exposure, and low-silver sinter pastes are an active development race between Indium Corporation, MacDermid Alpha, Henkel, Kyocera and Heraeus. Second, bundlingThe strategic move in this layer is selling the substrate, the sinter paste and the thermal interface as one qualified system. That raises switching costs enormously and is the reason these quiet Japanese and German franchises defend margin better than the wafer makers ever did.

Where WBG meets the 800VDC architecture

In the 800VDC data center architecture, wide-bandgap devices appear at every conversion stage. SiC handles the sidecar rectification and any solid-state transformer front end (and in the 2300/3300V class for medium-voltage interfaces). SiC also handles the primary side of the 800V→54V/12V board-level converter, with GaN on the secondary. GaN or advanced silicon handles the point-of-load VRMs delivering ~0.7V at thousands of amps into the GPU package. An 800VDC bus moving 140kW needs only ~175A, reported to cut copper requirements by ~45% against an equivalent 54V architecture. Cumulative chain efficiency can exceed 90% versus 70-85% for the legacy AC path. At gigawatt scale that difference is tens of megawatts released back to compute.

The content numbers are what make this investable, and management teams have started to disclose them. Infineon guides $12-15k of power semiconductor content per current 130kW AI rack, roughly $104 per kW, or ~$104k per MW. onsemi estimates content per next-generation 1MW rack has doubled from ~$50k to ~$100k, on ~$250M of 2025 revenue from these applications with high-teens sequential growth. Independent analysis puts power component content per rack rising ~4x from GB200 to Vera Rubin and ~11.5x to Rubin Ultra. Littelfuse reported 2025 data center design wins more than doubling year-over-year, with next-generation content opportunity "significantly more than double" current levels.

Who does what in the rack

Scale check: automotive is still the demand base

Everything above has been a data center argument, and a reader would be right to push back. AI data centers stay below the principal demand driver for wide-bandgap semiconductors today. Automotive is, by a wide margin. Published estimates put automotive at roughly 61% of SiC power semiconductor revenue in 2025 on one methodology and as high as ~81% of combined SiC+GaN device revenue on a broader one. Either way, the direction of EV production volumes still moves this industry's revenue more than anything happening in Santa Clara.

The case for focusing on data centers anyway rests on three points.

1. Growth rate over level. Automotive SiC is growing but decelerating against expectations. That is the demand miss that caused the glut. Data center WBG is compounding from a small base at rates no automotive programme can match: Infineon guiding AI-related revenue from €1.5B to €2.5B in one year, Wolfspeed's AI data-centre revenue more than doubling year-over-year in FY2026, onsemi's content per rack doubling. Marginal revenue growth is what re-rates equities and justifies capex, and it is now disproportionately coming from data centers.
2. Margin quality. Automotive SiC is a cost-down machine. Multi-year LTAs with annual price-down clauses, brutal qualification, single-digit-cent negotiations. Data center customers buy density, efficiency and time-to-deployment. They are less price-elastic because the power semiconductor is a rounding error against the GPU. Same die, better economics.
3. Architecture leverage. Automotive is a mature 400V/800V design space. Data center power architecture is being redesigned right now (800VDC, solid-state transformers, the elimination of the 48V intermediate bus) and design decisions taken in 2026-27 will lock supplier positions for a decade.

The framing for a model: automotive sets the industry's revenue base and its cycle; data center sets its growth rate, its mix, and its multiple. A reader building a forecast should size automotive first and treat the data center as the delta. A reader looking for where competitive position is being decided should watch the data center exclusively. The risk that follows is straightforward: this sector has swapped a demand concentration in one cyclical end-market (autos) for a growing concentration in another, more correlated one (hyperscaler capex).

The silicon incumbent

Any technology-substitution story needs the incumbent's case put properly, and in power electronics the incumbent is enormous. IGBTs and superjunction MOSFETs represent roughly $11.6-18.7B depending on scope, several times the size of the entire SiC device market, and are growing 10-12% annually in their own right. Within the broader power semiconductor market of roughly $60B in 2026, silicon still does the overwhelming majority of the world's power conversion. WBG remains the fast-growing minority of a still-silicon world.

Silicon also keeps improving specifically to defend itself. Toshiba's multi-gate IGBT architectures cite 24-28% lower turn-off loss (double-gate 24%; triple-gate 28% per Toshiba 2021 disclosures) than previous planar generations. Superjunction MOSFETs continue to improve the breakdown-voltage / on-resistance trade-off that was supposed to be their fundamental ceiling. Packaging innovation (double-sided cooling, embedded die) lifts silicon module performance without touching the die. Every generation of silicon improvement raises the bar that SiC's 3-5x lower switching losses have to clear economically, not just technically.

The substitution boundary is a moving price line. SiC wins where switching frequency, thermal headroom or system-level size reduction pay for the die premium: traction inverters, fast chargers, and now the 800VDC rectification stages where efficiency compounds across a gigawatt. Silicon holds everything else, and the wafer price collapse cuts both ways. It narrows SiC's cost gap, which accelerates substitution, but it also compresses the returns available to whoever wins that substitution. The bear case for WBG is SiC succeeding at prices that never justify the capital deployed to build it. That is what happened between 2022 and 2025, and nothing in the structure of the industry prevents a repeat.

What AI is worth to the wide-bandgap semiconductor industry?

Top-down forecasts for SiC and GaN are abundant and contradictory. SiC power semiconductors at ~$3.4B in 2026 growing ~25% CAGR to ~$10B by 2031 on one methodology; combined GaN+SiC at ~$4.1B in 2025 reaching ~$39B by 2035 on another. I build the number from scratch below, and I build it twiceThe two available methods disagree by a factor of three, and the disagreement is the most informative output.

Method A. Bottom-up from rack content

Infineon discloses $12-15k of power semiconductor content per current 130kW AI rack. Take the $13.5k midpoint and you get ~$104k per MW of IT loadonsemi independently puts content at ~$100k per next-generation 1MW rack. The two disclosures corroborate each other closely. Global data center power demand is running ~132GW in 2026 (up from ~104GW), with AI-optimised servers at ~31% of consumption. Roughly 18-20GW of new capacity is being added annually. Netting facility overhead to IT load (~70%) and taking the AI-relevant share of new build, I model ~8-10GW of AI IT-load additions in 2026At $104k/MW that gives ~$0.9-1.0B of rack-level power semiconductor content, of which WBG is perhaps 45-55%. Call it $0.4-0.6B.

Method B. Top-down from disclosed guidance

Infineon guides €1.5B of AI-related revenue in FY2026 and is described by Gartner as the company to beat in this segment. If its share of AI power semiconductors is 30-40%, the implied total market is €4-5B (~$4.5-5.5B) in 2026. Infineon separately sizes the AI power infrastructure opportunity at ~€12B by 2030. Applying a 45-55% WBG slice gives ~$2.0-2.9B of WBG device revenue in 2026.

Reconciling Method A and Method B

Method B is roughly 4x Method A, and the difference comes from definitions, not arithmetic. Method A counts only what is inside the compute rack. Method B counts the entire power tree: grid-side and facility conversion, UPS and switchgear electronics, PSUs, busbar systems, board-level converters and point-of-load regulation, plus service and replacement into the installed base. Infineon's own description of its AI portfolio spans "utility-scale power conversion to rack-level power supplies", which confirms the wider scope. There is also a timing effect: revenue recognised in FY2026 includes design-in and pre-build ahead of 2027 deployments.

I adopt the full-power-tree definition, which is the economically material boundary for anyone investing in this chain. That puts WBG device revenue from AI data centers at roughly $2.0-2.5B in 2026, with a central path to about $11B by 2030 (range $9-14B depending on the WBG share assumption and the pace of 800VDC adoption). Readers who prefer the narrow rack-only definition should divide by roughly four throughout. Full workings, including the scenario drivers, are in Annex §A6.

Profit pools: the inversion

The margin map of this industry has inverted over three years, and the inversion is where allocation decisions get made. In 2022, substrates were the scarce layer and carried 40-60% gross margins. Today, after the glut, merchant substrate margins have compressed brutally (Chinese suppliers reportedly selling near cost) and the layer is commoditising. Devices hold better (35-50% for qualified automotive and infrastructure parts) because the moat is now qualification and reliability data, above the wafer. Packaging materials (AMB substrates, sinter pastes) have become the best-defended layer at 30-45%, protected by qualification bundling and Japanese/German process depth. Modules and rack-level converters run 20-35%, with the AI-specific parts currently enjoying scarcity pricing that will normalize as OCP standardizes. Equipment (Axcelis, Aixtron, DISCO) retains 40%+ through the cycle, because both the boom and the capacity race require tools regardless of who wins.

The M&A chessboard

A consolidating industry emerging from a price war, with a demand wave arriving and several sub-scale specialists holding critical IP, is the most target-rich environment in semiconductors right now. The precedents are already substantial: Infineon / GaN Systems ($830M), Renesas / Transphorm ($339M), onsemi / Qorvo SiC JFET ($115M), onsemi / GTAT, ST / Norstel, SK Siltron / DuPont SiC, Power Integrations / Odyssey, Innoscience's $180M IPO. On the minority-stake path, Denso and Mitsubishi Electric's investment into Coherent's SiC business demonstrated that customers will fund capacity directly when supply security matters more than ownership.

Valuation framing

Three anchors for an IC discussion. Precedent multiples. Infineon paid ~$830M for GaN Systems at a reported high multiple of then-revenue: a capability price. Renesas paid $339M for Transphorm on similar logic. In a market where design-in position determines a decade of share, capability multiples are rational. Distressed asset pricing. Wolfspeed's restructuring effectively valued a vertically integrated 200mm SiC franchise (Mohawk Valley, Siler City materials, CHIPS support, 300mm capability) at the enterprise value implied by ~$1.5-2B of post-emergence debt plus a diluted equity stub. Against ~$10B+ of cumulative capex sunk into that footprint, the replacement-cost argument is stark. Against continued 6-inch price erosion, so is the caution. Strategic-scarcity premium. Anyone who wants qualified non-Chinese WBG capacity in the 2027-29 window has approximately five phone calls to make, and every one of those counterparties knows it.

Technology disruption watch list

Standards, controls and the policy layer

The four instruments that drive cash flows here are standards, controls, subsidies and tariffs. Device physics sets the ceiling; these four set the timing. Qualification standards (AEC-Q101 for automotive, JEDEC reliability suites, and the emerging and still immature expectations for hyperscale infrastructure) are the real moat. They are why nameplate capacity and sellable capacity diverge. Export controls run both ways: US restrictions on advanced equipment into China, and China's gallium controls running the other direction, with the added wrinkle that Wolfspeed's CHIPS-funded assets come with US strategic strings that constrain who could ever buy them. Industrial policy is writing cheques at scale: CHIPS Act grants and DOE loans in the US, the EU Chips Act behind ST's Catania and Bosch's Dresden, the ~€530M Czech package for onsemi, and China's national IC fund committing reported multi-billion sums into SiC. Materials regulation (the EU Critical Raw Materials Act, REACH restrictions reshaping baseplate metallization, ECHA scrutiny of die-attach chemistries) determines which processes survive in Europe. Policy operates as a primary determinant of who has capacity in 2029; background-context framing understates it.

Trade-offs, winners and losers

• SiC vs GaN. Complementary today, competitive at the boundary tomorrow. Vertical GaN and GaN-on-SiC push upward in voltage. SiC trench devices push downward in cost. The 650-1200V band is where they will genuinely fight, and it sits where a lot of data center content converges.
• Vertical integration vs fabless. The glut rewarded integration (owning cheap internal wafers when merchant prices collapsed) but punished the capex. Post-glut, with substrates cheap and abundant, the fabless model looks materially better than it has in a decade. That is a large part of why Navitas' asset-light pivot is working.
• Deflation vs volume. Every device-level improvement (trench, 200/300mm, cold split, engineered substrates) is deflationary per die. The industry grows in revenue only if volume outruns ASP erosion. AI helps enormously because data center content per rack is rising faster than device prices are falling, for now.
• Winners. Infineon (breadth, scale, AI design-ins, "30-30" ambition), Navitas (design-in position vs size), the equipment layer (Axcelis, Aixtron, DISCO), the packaging-materials houses (Rogers, Heraeus, Kyocera, Denka, Mitsubishi Materials), the Japanese module incumbents if MV-DC and SST arrive, and a recapitalized Wolfspeed if AI mix outruns the 6-inch price war.
• Pressured. Merchant substrate pure-plays without captive demand, sub-scale Chinese substrate makers heading into domestic consolidation, GaN specialists without a foundry partner or a design-in, and any business model that assumed 2022 substrate pricing would persist.
• The dominant risk. An AI capex correction. Automotive demand is no longer the swing factor it was. This industry has re-levered itself to hyperscaler capital expenditure, which is a stronger driver in 2026 but also a more correlated one.

Ten leading indicators to watch

1. Wolfspeed's AI revenue mix and 200mm utilization. The clearest single read on whether the restructuring thesis works.
2. Infineon's progress against "30-30" and its AI revenue trajectory past €2.5B. The sector's benchmark disclosure.
3. Chinese 6-inch spot pricing. If it stabilizes above ~$250, the worst is over. If it keeps sliding, more consolidation.
4. 200mm yield disclosures. The gap between nameplate and effective capacity closes here first.
5. onsemi's GaN entry. Organic or by acquisition. Either way it reprices the GaN specialists.
6. Navitas 800V-to-6V design wins converting to volume. Validates the elimination of the 48V stage and the GaN content thesis.
7. AMB Si₃N₄ lead times and Chinese qualification announcements. The next chokepoint's early warning.
8. Gallium export policy moves. The GaN thesis's single biggest exogenous risk.
9. SST pilot deployments in data centers. Pulls 1700-3300V SiC demand forward by years if it lands.
10. Any national-security review triggered by a Wolfspeed asset sale. Tells you whether Western WBG capacity is genuinely for sale.

Sustainability: a strong story with three honest caveats

The headline case is genuinely excellent and rarely disputed. Wide-bandgap devices exist to reduce conversion losses, and in a data center context the arithmetic is large. An 800VDC chain built on SiC and GaN can exceed 90% cumulative efficiency against 70-85% for the legacy AC path. At gigawatt scale that difference is tens of megawatts that stop becoming heat and start becoming compute. Multiply across the EV and renewables fleets and WBG is one of the few semiconductor categories whose use-phase savings unambiguously dwarf its manufacturing footprint.

The caveats deserve equal billing. First, crystal growth is energy-intensive. PVT sublimation runs at ~2,300°C for a week or more per boule, making SiC substrate manufacturing materially more energy- and carbon-intensive per wafer than silicon. That is a real embodied-carbon burden even if the lifetime balance is favourable. Second, the fab chemistry runs dirty. WBG fabs use fluorinated etch gases with very high global-warming potentials and are exposed to the tightening regulatory perimeter around PFAS in semiconductor manufacturing. GaN adds gallium and, in some processes, arsenic-adjacent handling requirements. Third, the packaging layer brings a precious-metal dependency. Sintered-silver die attach ties the module cost base and its supply-chain footprint to silver, which is why silver-free AMB substrates and low-silver pastes are being developed as much for supply resilience as for cost. (I have not cited a specific lifecycle-assessment figure here because I could not verify one to a standard I would defend. The directional statements above are well established. The precise multiples stay less settled.)

The public-market exposure map

For analyst readers, the listed vehicles touching each layer. Mapping only. Nothing here is a recommendation, and exposure purity varies enormously.

Where the industry is now

For five years, the WBG bull case was electric vehicles. The industry sized capacity to that thesis. The EV ramp then underperformed the forecasts, and the resulting glut took the industry's founding US pure-play through bankruptcy court.

What comes out the other side is a leaner, consolidated chain, better capitalised in the places that matter. The demand it now serves is AI data center power, which pays for density and efficiency in ways the automotive customer never did.

Wafers have commoditised. The value has moved above them. The profits sit in the devices whose qualification data is the moat, in the packaging materials the models routinely under-count, and in the equipment whose tools get bought whichever fab wins.

For operators, power semiconductor supply is no longer the binding constraint it was in 2022. Design for the architecture you want. For investors, the money in this cycle went to the equipment makers and the packaging houses more than the wafer producers, and the setup for the next cycle points the same way.

Annex: how every derived number was built

Everything in this piece is either published (traceable to a named source), derived (calculated from published inputs, with the arithmetic shown below), or estimated (my judgement, flagged as such). This annex covers the second and third categories so any reader can rebuild, challenge, or discard the numbers.

§A1. SiC wafer price observations

Status: published observations, mixed metrics. The chart plots five discrete datapoints, and they measure different things.

Known weakness. The apparent uptick from end-2023 to mid-2024 is an artefact of switching from epi-wafer to substrate quotes between sources. Do not read the pattern as a trend line. Separately cited: 6-inch epi wafer average prices fell ~15.9% between 2023 and 2024, and 8-inch declines exceeded 60% (industry compilation, 2025).

§A2. SiC substrate market share

Status: published, 2024 vintage. TrendForce (May 2025) on 2024 substrate revenue of ~$1.04B (down 9% YoY): Wolfspeed 33.7%, TanKeBlue 17.3%, SICC 17.1%, Coherent 13.9%. Residual 18.0% is my arithmetic (100 minus the four published shares), covering SiCrystal/ROHM, Resonac, SK Siltron, Sumitomo Electric, Synlight, JSG and others. Separately, Mordor (2026) states the top five (Wolfspeed, Coherent, ST, ROHM, SK Siltron) controlled about half of global capacity in 2025. That is a different metric on a different basis and stays unreconciled here.

§A3. Power GaN market share

Status: two published anchors, positions 2-5 estimated. Published: Innoscience ~30% share of power GaN (Yole Group, Sep 2025, on 2024 data); top five ≈88% of revenue (Intel Market Research, on 2024 data). Derived: the residual 58 points across positions 2-5 were allocated as Infineon 18 / Power Integrations 15 / Navitas 13 / EPC 12, with 12 points left for Renesas-Transphorm and the tail. Ordering follows Yole's qualitative description of the competitive set. The individual values are my estimates and should not be quoted as data. Corroborating context: Renesas' Transphorm business was described as on track to exceed $100M of GaN revenue by 2026, which is consistent with a mid-single-digit to low-double-digit share of a market of this size.

§A4. SiC device market share

Status: published ranking, interpolated values. Published: TrendForce 2023 ranking gave ST 32.6% with the top five at 91.9% of revenue, order ST > onsemi > Infineon > Wolfspeed > ROHM, with ROHM at 5.0% (~$186M). Derived: I allocated the intervening positions as onsemi 18 / Infineon 17 / Wolfspeed 14 to fit both published constraints, leaving ~14% for all others. Only ST's and ROHM's figures are published. The middle three are interpolation. Note that Mordor's 2026 commentary gives a different top five for the SiC power semiconductor market (Infineon, ST, Wolfspeed, onsemi, ROHM at >90% combined) and GM Insights puts Infineon at >19.5% of the broader power semiconductor market in 2025. Different universes.

§A5. End-market split

Status: two published figures on different bases, shown side by side deliberately. Mordor Intelligence: automotive 61.45% of the SiC power semiconductor market in 2025. Intel Market Research: automotive ~81% of the combined SiC+GaN power device market in 2024, projected to ~83.6% by 2032. The remaining category splits in the chart (industrial/energy, data center, other) are my estimates fitted to each source's automotive anchor and are illustrative only. The discrepancy is mostly scope: SiC-only versus SiC+GaN, and differing treatment of industrial/energy applications.

§A6. TAM model for WBG devices in AI data centers

Status: derived. Full workings below.

Published inputs. Content per rack: Infineon guides $12-15k per 130kW AI rack; $13.5k ÷ 0.13MW = $103.8k per MWonsemi: content per next-generation 1MW rack doubled from ~$50k to ~$100k per MWAn independent corroboration within 4%. Capacity: Gartner puts global data center power demand at ~132GW in 2026 (from ~104GW in 2025), with AI-optimised servers at ~31% of consumption in 2026 (from ~20% in 2025) rising toward ~50% by 2030. Build rate: JLL and others put new capacity additions at roughly 18-20GW annually through 2027-29, rising to ~31GW in 2029-30, with ~100GW added 2026-2030. McKinsey projects ~156GW of AI-related capacity by 2030.

Derivation of AI IT-load additions. Facility capacity additions ~18-20GW/yr (2026-27); AI-relevant share of new build assumed at 55-65% (well above AI's ~31% share of the installed base, because new build skews heavily to AI); therefore ~10-13GW/yr of AI facility capacity. IT load at ~70% of facility power (Brookings: servers ≈60% of DC electricity, ~75% in AI-optimised hyperscale) gives ~7-9GW/yr of AI IT-load additions in 2026, rising to ~14-18GW/yr by 2030 as both build rate and AI share increase.

Method A (rack-only). 8.5GW × $104k/MW = ~$0.88B of rack-level power semiconductor content in 2026. WBG share of that BOM assumed 45-55% (SiC in rectification and HV DC-DC; GaN in intermediate and some POL stages; silicon retains much of point-of-load and control), giving ~$0.40-0.49B.

Method B (full power tree). Infineon FY2026 AI revenue guidance €1.5B ÷ assumed 30-40% share gives implied market €3.75-5.0B (~$4.3-5.7B at 1.15 USD/EUR). WBG slice at 45-55% gives ~$1.9-3.1BMidpoint adopted: ~$2.2B for 2026.

Why they differ (4x). Method A counts only in-rack content. Method B captures the full chain from utility conversion through UPS/switchgear electronics, PSUs, busbars, board-level converters and point-of-load, which is how Infineon itself describes its AI portfolio, plus installed-base service and pre-build revenue recognised ahead of deployment. Neither is wrong. They answer different questions. The article adopts Method B and says so.

Scenario construction to 2030. Base case: AI IT-load additions growing to ~15GW/yr by 2030; WBG share of power BOM rising from ~50% to ~60% as 800VDC penetrates and SiC enters MV/SST stages; content per MW roughly flat in nominal terms (density-driven content increases offsetting ~8-12% annual device ASP erosion). Result: ~$11B by 2030. Bear case: AI capex air-pocket cutting additions growth by half, 800VDC adoption slipping a generation, WBG share stalling at ~45%. Result: ~$4.5B. Bull case: 1MW racks on schedule, SST pilots pulling 1700-3300V SiC forward, retrofit wave into the 2025-26 installed base, WBG share ~65%. Result: ~$16B. Cross-check. Infineon sizes the total AI power infrastructure opportunity at ~€12B (~$13.8B) by 2030. A WBG slice of 55-65% of that implies ~$7.6-9.0B, somewhat below my base case. The gap is my assumption that Infineon's framing captures its own addressable view (the full global market sits larger). A reader who prefers Infineon's framing should shade the base case down by 15-25%.

Sensitivity. The model is most sensitive, in order, to: (1) the WBG share of the power BOM (a ±10pt swing moves the 2030 base case by roughly ±$2B); (2) AI IT-load addition growth, itself gated by grid interconnect timelines discussed in Part IV: The Interconnect Stack (a 4-7 year US ISO queue is a real bear-case driver; (3) device ASP erosion, which could turn a volume boom into flat revenue if it runs above 15% annually.

Western hyperscale vs Chinese cloud split. The base-case TAM is global. Western hyperscalers (US, EU) source almost exclusively from Western/Japanese devices under strict provenance rules; Chinese hyperscalers (Alibaba, Baidu, Tencent, ByteDance) increasingly source domestic Chinese devices for the same reasons in reverse. The addressable-market split for Western device vendors is therefore materially smaller than the global TAM implies. Split shown below.

§A7. Profit pool / margin bands

Status: estimated. No source publishes gross margin by value-chain layer for this industry. The bands shown (substrates ~50% to 18%, epitaxy ~38% to 30%, devices ~35% to 42%, packaging materials ~32% to 38%, modules ~25% to 28%, equipment ~42% to 44%) are my judgement, built from company-reported segment margins where disclosed (Infineon, onsemi, Wolfspeed, Aixtron, Axcelis, Rogers, Coherent); the documented substrate price collapse (§A1) applied against broadly fixed cash costs; reported Chinese substrate selling near or below cost; and analogues from the lithium-ion materials chain where a scarce upstream commoditised faster than a qualified midstream. These are directional illustrations of a migration.

§A8. Content escalation index

Status: published, re-indexed. Source: The Diligence Stack (May 2026) estimates power component content per rack rising ~4x from GB200 to Vera Rubin and ~11.5x from GB200 to Rubin Ultra. I have simply set GB200 = 1.0 and plotted 1.0 / 4.0 / 11.5. This measures power components broadly, and it is one analyst's estimate (a manufacturer disclosure stays absent).

§A9. Other published figures used

• Wolfspeed restructuring. Debt reduced ~70% / ~$4.6B, maturities to 2030, cash interest down ~60%, filed 30 Jun 2025, emerged 29 Sep 2025, convertible holders ~95% of new equity, existing shareholders 3-5%. Source: Wolfspeed press releases and SEC Form 8-K (Jun. Sep 2025). FQ1 2026 per company 10-Q: revenue $196.8M, net loss $85.2M (from $119.8M), capex $103.9M (from $211.6M), cash + ST investments $926M, guidance $150-190M. Source: Semiconductor Today via EAM Vision (Nov 2025).
• Chinese substrate capacity. 460k (2022), 1.17M (2023), 2.22M (2024), 3.9M (2025E), 7.71M (2027E) units. CNY 50bn national IC fund commitment 2024-25. Source: industry compilations (2025) and Mordor (2026). Nameplate.
• 200mm economics. 2.2x more die per substrate, up to ~40% lower cost per unit, ~35% lower cost per wafer vs 150mm. Global average 200mm yield reported below 50%. Source: Mordor Intelligence and industry press (2025-26).
• Infineon. FY2026 AI revenue target €1.5B rising to €2.5B in FY2027. ~€12B AI power opportunity by 2030. FY2026 capex raised €500M to €2.7B. "30-30" ambition of 30% SiC share by 2030. Trench SiC superjunction claiming ~40% lower R_DS(on)×A. Named by Gartner as company to beat in AI data center power. Sources: Infineon disclosures, Reuters via Astute Group, 247WallSt, Semiconductor Today (2026).
• Navitas. 800V-to-6V power delivery board eliminating the 48V IBC stage, shown in NVIDIA MGX ecosystem, Computex Jun 2026. GlobalFoundries foundry partnership. PowerChip 200mm GaN-on-Si for 100V FETs. 2300V/3300V SiC sampling. High-power markets a majority of revenue for the first time in Q4 2025. Sources: Navitas press releases and SEC 8-K filings (2025-26).
• onsemi. Content per 1MW AI rack ~$50k to ~$100k. ~$250M 2025 revenue from these applications. Qorvo SiC JFET acquisition $115M (Jan 2025). ~€530M EU state aid for Czech SiC facility (Nov 2025). Sources: company disclosures and trade press.
• M&A precedents. Infineon / GaN Systems $830M; Renesas / Transphorm $339M; Innoscience IPO $180M. Source: Yole Group. onsemi / GTAT, ST / Norstel, SK Siltron / DuPont SiC, Power Integrations / Odyssey. Source: trade press.
• AMB substrates. Top eight ≈85% share (2023). Si₃N₄ >95% of AMB mix. Production split Japan 27.3% / Germany 24.6% / China 43.5%, China to ~57% by 2030. Heraeus ~15% share. Heraeus Condura.ultra silver-free product. Sources: Intel Market Research, Global Growth Insights, Heraeus Electronics (2025-26). Market size estimates range from ~$243M (2025) to ~$1.2B (2024) across sources on differing scopes. This spread is unresolved. I have quoted the range (picking one would overstate confidence).
• Silicon incumbent. IGBT + superjunction MOSFET market $11.6B (2025, Mordor) to $18.7B (2025, Metastat) depending on scope. ~10-12% CAGR. Total power semiconductor market ~$60B in 2026 (Mordor). Toshiba dual-sided multi-gate IGBT ~34% lower turn-off loss, as cited.
• 800VDC efficiency. ~175A at 140kW on an 800V bus, ~45% copper reduction vs 54V, chain efficiency >90% vs 70-85% legacy AC, board-level HV DC-DC at 97-98.5%. Source: Bristlemoon Research (Jun 2026).

What comes next

This is Part II of a six-part series on the AI power chain. Part I (The Capacitor Stack) traced how hybrid supercapacitors, EDLCs, MLCCs and silicon capacitors became scarce simultaneously under the 800VDC transition. Part III (The Thermal Stack) does the same for liquid cooling: cold plates, CDUs, immersion, and the shift from air to two-phase. Part IV (The Interconnect Stack) covers the copper and grid equipment that transmit the pulses these devices switch. Part V (The On-Package Delivery Stack) covers the 48V-to-0.8V last-mile conversion at the accelerator itself. Part VI (The Modular Datacenter Stack) covers the modular civil and electrical infrastructure needed to build hyperscale AI campuses on the schedule the sector requires. Same method throughout: name the players, size the layers, mark the chokepoints, adopt bottom-up TAM, and be explicit about what is published, derived and estimated.

For readers who want the underlying physics, manufacturing process flows and device cross-sections, see the technical companion: The Wide-Bandgap Stack: Technical Companion. For a company-level deep dive on the largest US SiC pure-play post-Chapter 11, its 10 kV MOSFET first-mover position, and the MV SST customer set, see Tech Spotlight 05: Wolfspeed's Second Act.