Market deep dive · AI data center power

The 800VDC transition has turned four component categories (hybrid supercapacitors, EDLCs, MLCCs, and silicon capacitors) into some of the most supply-constrained, strategically contested layers of the AI buildout. A layer-by-layer analysis of the technology, the market structure, the component supply chains beneath them, and the M&A chessboard forming above them.

Executive summary, eight findings.
  1. Energy storage is now a compute platform component, not a reliability appendix: ~20x storage step-up at Vera Rubin; capacitive shelves native to the 2027 Kyber/800VDC reference architecture.
  2. HSCs own the contested 10ms–10s window; the binding constraint is cell capacity (2026 demand ~2–3x supply), not demand or technology. EDLC carries 2026 deployments as the bridge.
  3. A bottom-up TAM build puts datacenter capacitive storage systems at roughly $0.8–1.4B in 2027, scaling toward $3–6B by 2030 in the base case, with assumptions stated and stress-testable (§TAM).
  4. Profit pools migrate: scarcity rent sits with cells and materials through 2027; systems/integration margin compresses fastest once OCP standardizes the shelf.
  5. The materials layer is tighter than the cell layer: Kuraray (cathode carbon), Nippon Kodoshi (separators), Sumitomo Metal Mining (MLCC nickel paste) are the unpriced chokepoints.
  6. China is the supply-side wildcard: 30–50% cost deltas vs. Japanese cells, held out of hyperscale sockets mainly by qualification friction and provenance rules, a moat, not a wall.
  7. The M&A window is open and closing: Musashi ES inside an auto-parts parent is the classic carve-out arbitrage. Tesla's $218M Maxwell deal (2019) is the haunting precedent benchmark.
  8. Batteries cannot retake the smoothing socket (a training workload is ~15M micro-cycles/year; no battery chemistry survives it), they defend only the minutes-scale autonomy socket.
33 kVStage 0 · The thesis
The AI Power Chain · six essays, one physical arc

The series walks a single physical path. It begins at the medium-voltage utility bus at the site fence, steps down through the substation and switchgear, arrives at the datacenter rack where 800V DC is stabilised by the capacitor stack, is converted by silicon-carbide switches to 48V, is distributed across the rack by copper busbars and whips, is stepped down again by multi-phase controllers on the accelerator board to 0.8V, and finally routed through the on-package power delivery network to a transistor gate drawing over 2,000 amperes. Waste heat from every conversion stage is removed by the thermal stack. The whole thing is packaged inside a factory-modular building because there aren't enough electricians to build it stick-frame. Six essays. One 800V → 0.8V staircase.

  1. Part I. The Capacitor Stack — 800VDC at the rack (you are here)
  2. Part II. The Wide-Bandgap Stack — SiC and GaN conversion
  3. Part III. The Thermal Stack — removing the waste heat
  4. Part IV. The Interconnect Stack — busbars and whips
  5. Part V. The On-Package Delivery Stack — 48V to 0.8V
  6. Part VI. The Modular Datacenter Stack — how the building gets built
800 V DC
Rack inlet · energy shelf~750 A busbar at the rack; the capacitive shelf absorbs the 10 ms–10 s transient before it hits the grid
The contested socketHSC / LIC cells & modules; EDLC bridge; Al electrolytic (incumbent, being displaced)
800 → 48 V
Power shelf DC-DCIsolated step-down inside the rack; feeds board voltage regulators
Bulk boardPolymer bulk; hybrid Al-polymer; Al electrolytic
48 → 0.75 V
Board POL & VRMPoint-of-load conversion on the accelerator PCB; µs–ms decoupling
Decoupling arrayMLCC arrays (thousands per accelerator); polymer tantalum
0.75 V · 4 kA+
In-package · under the dieSub-microsecond decoupling at the silicon boundary; the zone MLCCs cannot physically reach
Structural design-inSilicon capacitors (deep-trench); embedded MLCC
Indicative topology. Six distinct capacitor markets sit on one power path; each owns a different transient window and answers to different economics.
~20x
Increase in integrated energy storage, Vera Rubin vs. prior NVIDIA generation
600 kW
Kyber rack power, 2027, 800VDC at the rack inlet, ~750A busbar
2–3x
2026 AI-server supercapacitor demand vs. available manufacturing capacity
+15–35%
Murata MLCC price increases effective April 2026; peers followed
The forcing function: rack power density
kW per rack, NVIDIA flagship platforms, 2023–2029E
Source: NVIDIA roadmap disclosures (GTC 2025/2026), OCP; 2028–29 indicative. Author's compilation.

Rack power has grown more than 4x in two years, and the industry is openly designing for 1MW racks. Below ~200kW, conventional AC distribution and software smoothing suffice. Between 200–350kW, capacitive peak absorption becomes economically compelling. Above ~350kW, the entire 2027+ roadmap, the 800VDC architecture with native energy shelves becomes the default, and with it a new, large, and structurally growing demand pool for every layer of the capacitor stack.

STACKThe framework · Four markets, one problem

One pulsed load, four capacitor markets

The clean way to hold this space in your head is as a timescale ladder. Each rung is a distinct component market with distinct suppliers, cost structures, and competitive dynamics, and AI has tightened supply on every rung simultaneously, for the same root cause.

LayerTimescaleTechnology2026 market (est.)LeadersAI-era dynamic
In-packagens–µsSilicon capacitors, embedded MLCC~$1–2B broad; AI-substrate niche inflectingMurata/IPDiA, SEMCO, TSMCDesign-in via BSPDN
Board / POLµs–msMLCC arrays, polymer~$15–23BMurata, SEMCO, Taiyo Yuden, TDKShortage; +15–35% pricing
Power shelf bulkms–100msAl electrolytic / polymer → HSC migration~$8–10B Al-electrolytic categoryNippon Chemi-Con, Rubycon, Nichicon, PanasonicIncumbent being displaced up-shelf; polymer grows on-board
Rack / sidecar10ms–10sHSC (sweet spot), EDLC bridge~$1–3B supercap categoryMusashi, Panasonic, SkeletonDemand 2–3x supply
Bridge / BBU10s–minLi-ion BBUAdjacent (battery market)CATL, LGES, Samsung SDICoexists; fire-code capped
Campus BESSmin–hrsLi-ion LFPAdjacent (BESS market)Tesla, Fluence, SungrowInterconnect compliance
The timescale ladder: one pulsed load, six windows
Which device class owns each transient decade. The red rung is the socket AI created and where the supply gap sits.
Silicon caps · MLCCin-package / on-die
ns – µs
MLCC arrays · polymerboard / POL
µs – ms
Al electrolytic → HSCpower shelf bulk
ms – 100 ms
HSC (sweet spot) · EDLC bridgerack & sidecar
10 ms – 10 s
Li-ion BBUbridge to generator
10 s – min
Li-ion LFPcampus BESS
min – hrs
nsµsmssminhrs
Log-time layout, decades roughly evenly spaced. Each rung is a distinct component market, same problem at the load, different physics at each device class.
MLCCs and HSCs don't compete, they're the two ends of the same pulsed-load problem, and AI made both scarce at the same time.The stack thesis in one line
800 VLayer 1 · The energy shelf