Adi's Theses on AI infrastructure
The six canonical theses that run through the essays on adikumar.co, stated in full here with cross-references to the long-form work that develops each one. Written for readers who want the practitioner view in short form before working through the underlying essays.
The binding constraint on AI compute through 2030 has shifted from silicon supply to power infrastructure
Through 2030 the practical constraint on AI compute is running through power infrastructure rather than through GPU supply or model architecture. Transformer lead times measured in multi-year windows, capacity constraints at DLC vendors, wide-bandgap semiconductor throughput running below hyperscaler pull, and multi-year grid interconnection queues each bind more tightly today than accelerator availability does at hyperscaler scale.
The shift is structural rather than cyclical. Compute-side bottlenecks historically cleared on two-year software or fabrication cycles that hyperscalers and their customers could plan around. Infrastructure-side bottlenecks clear on the five to ten year timescale of new transformer capacity, nuclear restart PPAs, and wide-bandgap wafer investment. Capital-allocation frameworks built on the older tempo systematically underprice the infrastructure layer through 2030.
AI data centre power delivery is compressing from facility scale toward the accelerator package
The direction of travel runs from facility-level UPS and 415V AC distribution down toward package-level 0.8V multi-phase point-of-load conversion. Function that used to sit at facility infrastructure like UPS ride-through and PDU distribution is compressing into the rack, while function that used to sit at rack infrastructure like multi-phase converters and bulk capacitors is compressing further, onto the accelerator package itself. As the physical distance between grid interconnection and die shortens, the vendor stack reorganises around each newly-drawn interface.
The 800V DC transition is the most visible manifestation currently in flight, though the same compression is happening in on-package power delivery through backside power delivery network (BSPDN) adoption and in on-die energy buffering through silicon-capacitor integration. Hyperscalers vary in which specific interface they redraw first and with which vendor, but the direction of travel is consistent across Microsoft, Meta, Google, and Nvidia-reference designs.
800V DC covers two deployment architectures under a shared standardisation umbrella
Two deployment paths are marketed as 800V DC. OCP's Mt. Diablo (Microsoft, Meta, Google, v0.7.0 March 2026) rectifies in a rack-adjacent sidecar, with a default ±400V bipolar output and a permitted 800V unipolar option in the same spec. Nvidia's reference architecture rectifies at row scale and hands a unipolar 800V bus to the compute rack. The defining architectural difference: the sidecar keeps the conversion boundary beside the rack; the native architecture puts it at the facility perimeter. Both paths are being coordinated inside the OCP 800VDC subcommittee (August 2026), with common interfaces and system requirements rather than one prescriptive topology.
Capacity growth on its own would not have moved hyperscalers off 415V AC-UPS. The transition is driven by density economics that roughly halve copper mass at rack, by DC bus behaviour under pulsed GPU load-step that AC-UPS distribution cannot easily absorb, and by alignment between the Nvidia reference platform and the OCP standardisation work. The end-to-end efficiency gain depends on where the system boundary is drawn and which topology is being compared; the direction of movement is toward fewer conversion stages and lower distribution losses at MW scale.
Cooling architecture is migrating from facility infrastructure toward the accelerator package
Air cooling stops being physically viable above roughly 100 kW per rack at any reasonable facility PUE, which pushes single-phase direct-to-chip liquid cooling into the position of default architecture for AI training racks, with two-phase immersion sitting further out on the density curve for Rubin Ultra and custom silicon. Coolant chemistry sourcing, CDU architecture qualification, and the multi-year approval cycles for hyperscaler-qualified quick-disconnects have each become supply-side chokepoints as hyperscaler pull expands faster than qualified capacity comes on.
The 2025-26 cooling M&A pattern is consistent with that view. Eaton closed the Boyd Thermal acquisition in March 2026 for approximately $9.5B per company disclosures, Ecolab closed CoolIT out of KKR for approximately $4.75B in the same window, and Schneider took a majority position in Motivair while Vertiv built cooling capability through capability tuck-ins including Strategic Thermal Labs and PurgeRite. Strategic buyers are underwriting these transactions at multiples that only make sense if thermal capacity is being valued as a scarce strategic input to hyperscaler capacity growth rather than as a conventional services line item.
Value concentrates in qualification-gated component suppliers as rack power rises
Value concentration in the AI infrastructure buildout is running toward suppliers whose qualification cycles gate hyperscaler production timing. Categories like AMB silicon-nitride substrates for GaN packaging, sintered-silver die attach for high-temperature reliability, dry-break quick disconnects for cold-plate loops, and hyperscaler-approved coolant chemistry each carry qualification cycles of two to four years against a supplier set of typically three to the vendors. That qualification barrier tends to survive even where the underlying technology moves toward commodity pricing, because the risk of respecifying an approved bill of materials mid-buildout falls disproportionately on the hyperscaler rather than on the supplier.
For AI infrastructure PE, the practical implication is that returns tend to concentrate in the qualification-gated positions that scale linearly with hyperscaler capex without commoditising on the same timeline. The more visible capacity-expansion trades on hyperscaler-adjacent operators capture a smaller share. Japanese and German industrial suppliers hold disproportionate share of the specific qualification-gated categories that appear on hyperscaler approved-vendor lists across power, cooling and packaging.
Load-side flexibility is a capacity-market product priced against interconnection acceleration
Hyperscale AI clusters in interconnection-constrained regions face queue durations of four to seven years for gigawatt-scale campuses in PJM, ERCOT, MISO and CAISO. The load-side flexibility layer that has emerged in 2025-2026 (battery-integrated microgrids, gas-fired behind-the-meter generation, software-coordinated training curtailment) clears economically because the compressed queue is worth orders of magnitude more than the avoided energy cost during a curtailment event. Idling advanced accelerators to escape peak-price hours is a strictly cash-dilutive trade on marginal economics; accepting curtailment to bring gigawatts of load online three years earlier turns the same behaviour into the most valuable capacity product in the interconnection stack.
For AI-infrastructure capital, this reframes the underwriting question. Vendors selling load-flex technology (Emerald AI's control layer, Verrus's battery microgrid, Enchanted Rock's modular gas) are not selling energy-cost savings. They are selling a bankable capacity right that translates a technical flexibility claim into utility-recognised accreditation. The layer that becomes the interoperability standard between hyperscaler workload schedulers and grid operators captures the disproportionate share of that value over a five-year horizon.