The On-Package Delivery Stack: circuit design, physics, process
A deeper walk through IR drop budgeting, multi-phase current sharing, backside power etch flows, and the design tooling that keeps an 0.8V rail stable across 2,250 amperes and thousands of transient domains.
Section 1: The IR drop budget, from first principles
The tightest number in AI silicon design is the transistor supply voltage tolerance. On a 3nm process, a nominal 0.75V core rail typically has a tolerance window of ±5% of nominal, or ±37.5mV. That number has to cover four independent effects: DC IR drop across the power delivery network, AC ringing on step-load transients, process variation of the transistor threshold, and thermal drift over the operating temperature range. The DC IR budget that the power delivery network is allowed to consume is therefore not ±37.5mV. It is closer to ±15–20mV after the other three effects have taken their slices.
Now do the resistance math. If an accelerator draws 1,800W at 0.8V, that is 2,250A of DC current. Holding IR drop below 15mV at 2,250A requires the total DC path resistance from the board-level VRM output to the transistor gate to be:
Six and two-thirds micro-ohms across a path that spans centimetres of substrate copper, millimetres of interposer routing, tens of micrometres of on-die metal stack, and a stack of TSVs and micro-bumps in between. The individual budget components look like this on a typical modern design:
Two observations from that decomposition. First, no single segment dominates the budget; the design is a distributed optimisation problem, not a single-choke-point problem. Second, the segment that scales worst with current is the on-die metal stack, because its resistance is set by the transistor node's minimum metal pitch, which shrinks as node scales, driving resistance up quadratically at the smallest lines. This is the physics that pushes the industry toward backside power delivery: BSPDN moves the highest-current segments off the tightly-pitched front-side metal and onto a separately-fabricated back-side stack that can be routed with much wider, thicker metal.
Why R matters more than L on a DC rail (and vice versa on transient)
Power delivery network analysis operates in two regimes. In steady state, the network is a distributed resistor and R alone determines DC IR drop. On transient (a step-load event where the processor's current consumption changes by hundreds of amperes within a nanosecond), the network is a distributed R-L-C, and the impedance seen by the load includes the reactive terms. A modern accelerator PDN targets a flat impedance profile from DC up to several hundred megahertz, and every violation of that profile shows up as voltage ringing at the transistor.
Meeting 500 µΩ impedance flatness from DC through 200MHz requires a hierarchical decoupling capacitor architecture. Bulk aluminium electrolytic capacitors at the VRM output handle DC through 10kHz. Ceramic capacitors on the motherboard handle 10kHz through 1MHz. Package-mounted MLCCs handle 1MHz through 30MHz. On-package deep-trench capacitors (integrated into the substrate or the interposer) handle 30MHz through 300MHz. And on-die MOS-capacitor arrays handle 300MHz and above. Each capacitor class has to be sized and placed so that its impedance region overlaps its neighbour with no resonant peak between them. Getting this wrong is the second most common cause of transistor throttling on new accelerator silicon, behind thermal throttling.
