The Grid-to-Chip framework: stage-by-stage series covering P1 Electrons through P5 Rack-to-gate
The AI-DC battery is migrating through six economic roles (R1 backup, R2 ride-through, R3 power smoothing, R4 peak management, R5 grid services, R6 grid-forming). Each stage carries a different vendor cohort, revenue mechanism and regulatory gate. Screen for R-stage exposure before chemistry.
Meta's OCP Mount Diablo spec commoditises the AI rack integration layer. Nvidia Kyber holds it proprietary. The contest allocates rack-integration margin across four vendor content planes.
An investment framework for the reclassification premium between firm AI capacity and firm-plus-flexible AI capacity. Five control models, three monetisation channels, and how time-to-power NPV can outweigh grid-services revenue in queue-constrained regions.
Every new power architecture destroys one conversion layer and creates another. The investable question is where the value migrates. SiC + GaN + POL + on-package IVR, mapped to Nvidia's 800V direction of travel.
Efficiency is migrating from ESG preference to procurement constraint. EU EED reporting → rating → minimum standards; Singapore DC-CFA2 allocation gate at PUE ≤ 1.25; US state mosaic (Virginia, Oregon, California). Vendor implications on UPS topology, PDU efficiency, cooling-electrical co-design.
Hall BESS as distinct P4.2c asset. Wholesale grid-services asset that happens to sit in a data hall. Revenue stack across cost avoidance, ancillary services, capacity, demand response. Vendor set: Tesla Megapack, Fluence, Powin, Sungrow, Wärtsilä. Contract structure is the killer question.
Standalone deep-dive on P4.2b UPS battery / BBU. LFP dominant, NMC niche, nickel-zinc pilot cohort. Killer thesis: pricing power migrates from UPS OEM to cell supplier over the decade. Trade-policy overlay (Section 301, 45X FEOC), 800V DC BBU migration, three-tier vendor set.
Fourth stage of Grid-to-Chip. Four vintages: V1 legacy AC, V2 hybrid 800V DC sidecar (H2 2026), V3 row-level 800V DC busway (2027), V4 native 800V DC facility. Killer thesis: the P4 cycle is a relocation of the power-conversion boundary, not a UPS replacement cycle.
Third stage of Grid-to-Chip. P3.1 site power transformer (HV to MV, 48-60+ mo lead times), P3.2 MV distribution, P3.3 hall conversion (SST vs conventional), P3.4 hall interface. 800V DC changes where conversion happens; SSTs sit at the intersection.
Second stage of the Grid-to-Chip framework. P2 as grid access globally. IEA 2.5+ TW queue worldwide. Five regime archetypes: ISO/RTO, VIU, TSO/DSO, state allocation, hybrid infrastructure. Three sub-problems. US deepest case study; UK, EU, APAC, MENA.
The first stage of the Grid-to-Chip framework. P1 is a contract, not a machine. Three-tier vendor taxonomy, 2024-2026 hyperscaler comps, per-tier scorecards with worked aggregates, falsification triggers, watch calendar. Sequencing beats archetype selection.