How does the Nvidia 800V DC architecture affect the P5 vendor set?

Directly. An 800V DC rack input requires a high-ratio intermediate conversion from 800V down to a low-voltage rail (12V, 48V or 54V depending on architecture). Nvidia Kyber uses 64:1 LLC to 12V near the accelerator. The high-voltage stage is a strong SiC candidate; GaN becomes increasingly competitive at the board / near-die stage.

Is SiC or GaN going to win at P5?

Both, in different sweet spots. SiC is the strong candidate for higher-voltage stages (400V+); GaN is increasingly competitive at mid-voltage and where switching-frequency requirements rise. Complementary rather than head-to-head substitutes across most of the P5 stack.

Which vendor leads the P5 vendor set?

Infineon leads the Tier 1 composite on AI-accelerator content, technology breadth and manufacturing scale. Vicor leads on pure-play design-win momentum. MPS leads on POL / VRM content growth. Analog Devices (post July 2026 Empower acquisition) is uniquely positioned across both POL and on-package IVR sides of the cascade.

What is on-package IVR and why does it matter?

Integrated voltage regulator built onto the accelerator package itself, displacing discrete board-level POL converters. Higher efficiency and lower rail impedance. Commercial scale currently limited. Analog Devices acquired Empower Semiconductor in July 2026 for approximately $1.5 billion. Earlier-than-expected commercialisation would displace board POL content.

What is the P5 killer thesis?

Every new power architecture destroys one conversion layer while creating another. The investable question is where the value migrates. Nvidia's 800V material states the direction of travel explicitly: fewer conversion stages, lower losses, direct path to 800V distribution. Screen the migration first, the technology second.

Grid-to-Chip P5 · Rack to Gate: SiC, GaN, POL and the last conversion cascade

29 August 2026 · 43 min read · Updated 6 Oct 2026

Grid-to-Chip P5 Rack to gate: conversion cascade from 800V DC rack input through 48V intermediate, 12V board, ~1V POL to accelerator die — The P5 cascade. From Nvidia MGX 800V DC rack input through intermediate, board and POL stages to the transistor gate.

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