Question 1. Is the target a Tier 1 provider, a Tier 2 supplier or a Tier 3 emerging platform?

The three tiers have different underwriting disciplines. Do not apply a Tier 2 lens to a Tier 3 name or vice versa. Tier 3 SST pure-plays require pre-commercial underwriting frameworks; Tier 2 conventional MV vendors require order-book and bottleneck frameworks.

Question 2. What is the target's exposure to the power-transformer bottleneck?

Vendors on the constrained side of the bottleneck (Hitachi Energy, GE Vernova, Siemens Energy) capture different economics from vendors on the alternative side (SST pure-plays).

Question 3. What is the target's position in the Nvidia 800V DC ecosystem?

SST pure-plays engaged in the Nvidia MGX qualification chain are exposed to a specific commercial-milestone timeline. Conventional MV vendors are less exposed to Nvidia's specific architectural moves.

Question 4. What is the exposure to modular vs stick-built substation trends?

Modular substation growth benefits specific vendors with prefabrication capability. Stick-built retains a share of larger and more complex campuses.

Question 5. What is the P2 anchor for the target's project pipeline?

P3 vendor demand depends on P2 interconnection resolution. Vendors whose customer projects are concentrated in constrained ISOs face higher project-timing risk.

Question 6. What is the P4 downstream architecture assumption?

The hall-level power specification (48V DC, 800V DC, LV AC) affects the MV to hall-input transformer selection. Vendors with SST DC-output capability are naturally positioned for the 800V DC transition.

Grid-to-Chip

Grid-to-Chip P3 · Campus Power: MV distribution, SSTs and the power-transformer bottleneck

27 August 2026 · 43 min read · Updated 30 Aug 2026

Grid-to-Chip P3 Campus Power feature: MV distribution stack from site substation through MV distribution to hall input, with SST pure-plays and three-tier vendor taxonomy footer — The P3 stack: P3.1 site substation (HV to MV), P3.2 MV distribution, P3.3 hall conversion (MV to LV or MV to 800V DC via SST), P3.4 hall interface. The power-transformer bottleneck sits at P3.1.

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