Grid-to-chip: the AI power pathway, defined

FRAMEWORK · DEFINITION

Grid-to-chip: the AI power pathway, defined

Grid-to-chip is the end-to-end power pathway from the utility interconnection to the accelerator die inside an AI server rack. The pathway contains five physical layers and a software envelope that monitors and controls them.

Definition

Grid-to-chip is a decomposition of AI data-centre power delivery. It covers every component between the point where utility electrons enter a campus and the point where conditioned current reaches a chip package.

Grid-to-chip is the operational name for the pathway. The AI Power Chain framework is the formal decomposition of the same scope, mapping vendors, standards and lead-time exposure per layer.

Grid-to-chip voltage flow Seven voltage conversion stages from utility grid transmission at up to 500 kV down to point-of-load regulation at 0.65V, with representative vendors at each stage. Stages grouped by P3 Campus power, P4 Hall power, P5 Rack to gate. GRID-TO-CHIP · POWER FLOW · 2026 The AI power pathway, end to end Seven voltage conversion stages from utility grid to accelerator die. GRID INTERCONNECT345 kV→ACCELERATOR DIE0.65 V~ 5 ORDERS OF MAGNITUDE · SEVEN CONVERSION STAGES · AC → DC IN THE HALL ▸ P3 · CAMPUS POWER 1 115 – 500 kV AC · 3-PHASE utility transmission Grid transmission HV AC backbone from generation to the campus substation. Long-run cables, interface transformers, protection and metering. Hitachi EnergySiemens EnergyGE VernovaMitsubishi ElecPrysmianNexans step-down to 34.5 kV AC 2 34.5 kV AC · STEP-DOWN campus substation Campus substation Grid HV to campus MV step-down. Large oil-immersed transformers, protection relays, GIS or AIS switchyards. The lead-time bottleneck. Hitachi EnergySiemens EnergyMitsubishi ElecHyundai ElecHyosung HIWEG step-down to 13.8 kV AC 3 13.8 kV / 4.16 kV AC · MV DISTRIBUTION on-campus switchgear MV distribution + switchgear On-campus medium-voltage distribution to each data hall. Breakers, switchgear lineups, protection, metering, arc-flash containment. ABBSchneider ElecEatonSiemens SIGE VernovaS&C Electric ▸ P4 · HALL POWER AC to DC conversion · HVDC transition 4 800 V DC (legacy: 480 V AC) AC → DC CONVERSION SST or rectifier AC-to-DC rack feed Rectification or solid-state transformation from MV AC to the rack DC bus. The HVDC transition point. Nvidia 800V and OCP Mt Diablo push the boundary deeper into the data hall. Delta ElectronicsVertivEatonSchneider ElecABBHitachi Energy ▸ P5 · RACK TO GATE step-down to 48 V DC rack bus 5 48 V DC (OCP OR v3, some 54 V) DC · RACK BUS power-shelf output Rack DC bus Power-shelf outputs distributed down the rack to compute trays over a copper busbar. OCP Open Rack v3 is the dominant standard. Delta ElectronicsAcBelLite-OnFlex PowerBel PowerChicony step-down to 12 V DC intermediate bus 6 12 V DC DC-DC · BOARD IBC isolated bus converter Board intermediate bus 48V DC to 12V DC on the server board. Isolated bus converter (IBC) or factorised BCM. Vicor's architecture split happens at this stage. VicorMonolithic PowerInfineonAnalog DevicesFlex Power ModBel Fuse multiphase buck to the die 7 0.65 – 1.8 V DC POL · MULTIPHASE 400 – 1000 A per die Point-of-load regulators The final step. Multi-phase buck VRMs feed the GPU or CPU core at 400-1000A, with the regulator placed on the socket or in-package. GB300 and Rubin generations push 2000A per die within reach. Monolithic PowerRenesasInfineonAlpha & OmegaTexas InstrumentsSTMicro IVR: Ferric (indep.) · Empower (ADI) · Infineonhyperscaler-internal: Google · Meta · Amazon 0.65 V at 1000 A to accelerator die ACCELERATOR DIE GB200 · GB300 · Rubin 0.65 V @ 1000 A per die, multi-rail, per-core regulation Figure 1 · Grid-to-chip voltage flow with representative vendors per stage. Vendor lists are illustrative not exhaustive. Voltages correspond to the Nvidia 800V HVDC + OCP Open Rack v3 architecture; legacy sites still run 480V AC rack feeds. adikumar.co · Normalised Alpha · 2026-10-12
Figure 1. Grid-to-chip voltage flow. Seven conversion stages from utility transmission at 115–500 kV AC down to point-of-load regulation at 0.65V @ 1000A per die. Stage groupings follow the P3 Campus power · P4 Hall power · P5 Rack to gate decomposition. Representative vendors shown per stage.

The five physical layers

  1. P1 · Electrons. Firm generation sourced for the AI campus. Utility PPAs, behind-the-meter gas microgrids, nuclear-restart hyperscaler deals, SMR candidates. The point at which a reserved electron becomes available to the load. Read the P1 essay →
  2. P2 · Grid access. Connection rights, interconnect queue positions, FERC and ISO transmission regimes, grid-interconnection studies. The point at which capital converts into a legal right to deliver load. Read the P2 essay →
  3. P3 · Campus power. MV distribution, solid-state transformers, substation design, and the power-transformer lead-time bottleneck. The point at which campus-level voltage conversion happens. Read the P3 essay →
  4. P4 · Hall power. The hall-storage architecture. BESS, flywheel UPS, static UPS, and the relocation of the power-conversion boundary from external utility into the data-centre hall. The point at which ride-through and peak smoothing happen. Read the P4 essay →
  5. P5 · Rack to gate. 800V DC distribution, isolated DC-DC converters, SiC and GaN wide-bandgap stages, and the point-of-load conversion cascade down to the chip package. The point at which high voltage becomes 0.6V at the die. Read the P5 essay →

The grid-to-chip software architecture

The grid-to-chip software architecture monitors, controls and orchestrates the five physical layers. Measurement runs from utility-interface meters through SCADA on campus and hall equipment to rack- and board-level BMC telemetry. Control runs from grid-code dispatch through DC-microgrid energy management down to converter-stage FPGAs.

Grid-to-chip simulation is the end-to-end modelling discipline that spans the pathway. Vendors use it to spec campus equipment before procurement. Investors feed it return-model inputs to stress scenarios. Operators test fault response against it before commissioning. The simulation surface is where power engineers, control engineers and data-centre operators converge on a single model of the pathway.

Why grid-to-chip is the right unit of analysis

  • Single scarcity envelope. If any one layer is capacity-constrained, the whole pathway is capacity-constrained. The slowest layer sets the campus completion date.
  • Cross-coupled capital stacks. The investable surface at each layer has its own payback and risk profile, but the capital stacks reference each other. A hyperscaler PPA at P1 only closes if P5 ships Blackwell-class racks on schedule.
  • Standards propagation. OCP Open Rack v3, Nvidia MGX, 800V DC adoption, FERC Order 2023, and ISO interconnection reform all pin layer-to-layer compatibility. Changes at one layer force changes several layers away.

Related frameworks

Grid-to-chip is the operational name. The following definition pages treat the same scope under different analytical lenses:

Where to start reading

Suggested entry points:

Grid-to-chip is the author's operational naming for the AI power pathway. Scope and layer boundaries match the AI Power Chain framework. All layer essays and the full framework walk are indexed above.