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The On-Package Delivery Stack: Technical Companion
IVR magnetics, thin-film substrates, high-density capacitors and the qualification-gated architecture of on-package power delivery.
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The On-Package Delivery Stack: How 48V Becomes 0.8V at 2,250 Amperes
How 48V becomes 0.8V at the chip die: multi-phase POL, IVR, on-package power delivery, and why the foundries hold the strategic value pool.
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The Interconnect Stack: Technical Companion
Where the market essay named the vendors and quantified the lead times, this piece explains the physics. Why voltage steps up, how a 400-tonne transformer moves 300 MW at 99% efficiency, why SF6 became standard and why it is being phased out.
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The Interconnect Stack: Transformers, Switchgear and the Grid Equipment That Gates the AI Buildout
Grid interconnect is the binding constraint on AI. Transformer lead times doubled since 2023. Hyperscalers now build own generation to escape 4-7 year utility queues.
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The Capacitor Stack: Technical Companion
Where the market essay named the vendors, this piece explains the physics. What a farad actually is, why HSCs beat batteries on 10-second pulses, why MLCCs derate under DC bias, and why a fifty-cent film cap decides whether an 800VDC rack survives its own noise.
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The Thermal Stack: Technical Companion
Where the market essay named the vendors, this piece explains the physics. What 1,000 W/cm2 at the die actually means, how a hundred-dollar coupling either saves or destroys a rack, and where cooling is going next.
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The Wide-Bandgap Stack: Technical Companion
Where the market essay named the players, this piece explains the physics. What wide bandgap actually means, why SiC and GaN outperform silicon at the same voltage, and how a boule of vapour-grown crystal becomes a switch that runs at 800V and 200kHz. Cross-sections, process flows, roadmaps.
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The Thermal Stack: How Heat Became the Binding Constraint on AI Compute
Every watt delivered to a GPU comes back as heat, and at 600kW per rack there is nowhere for it to go but water. Layer-by-layer analysis from die to dry cooler.
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The Wide-Bandgap Stack: Boom, Bust, and the Rebuild of AI's Power Semiconductor Chain
SiC and GaN are the enabling materials of 800V data centres. Boom, 60% price collapse, the Wolfspeed Chapter 11, and what comes next. Crystal boule to gate driver.
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The Capacitor Stack: How Energy Storage Became Core Compute Infrastructure
Four capacitor categories are the binding AI supply constraint: HSCs, EDLCs, MLCCs, silicon caps. Layer-by-layer on pricing, capacity, and the qualified vendor list.
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The architecture map (where every stage lives, who builds it, what's standardized) (3/13)
The AI data centre power train is six stacks, not one. Where each stage lives, who builds it, what is standardised. Reference map for architects speccing new AI campuses.
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Two architectures wearing the same name (and how the industry is converging) (2/13)
The trade press writes about 800 VDC as one architecture. There are two, they behave differently in retrofit, and hyperscalers are choosing between them right now.