How DD findings translate into the transaction paper. Structure choice, R&W with insurance, escrow with DD-informed carve-outs, earnout mechanics.
Every new power architecture destroys one conversion layer and creates another. The investable question is where the value migrates. SiC + GaN + POL + on-package IVR, mapped to Nvidia's 800V direction of travel.
Efficiency is migrating from ESG preference to procurement constraint. EU EED reporting → rating → minimum standards; Singapore DC-CFA2 allocation gate at PUE ≤ 1.25; US state mosaic (Virginia, Oregon, California). Vendor implications on UPS topology, PDU efficiency, cooling-electrical co-design.
Hall BESS as a distinct asset class. Wholesale grid-services asset deployed inside a data hall. Revenue stack across cost avoidance, ancillary services, capacity, demand response. Vendor set: Tesla Megapack, Fluence, Powin, Sungrow, Wärtsilä. Contract structure is the killer question.
Standalone deep-dive on the lithium UPS battery / BBU. LFP dominant, NMC niche, nickel-zinc pilot cohort. Killer thesis: pricing power migrates from UPS OEM to cell supplier over the decade. Trade-policy overlay (Section 301, 45X FEOC), 800V DC BBU migration, three-tier vendor set.
Fourth stage of Grid-to-Chip. Four vintages: V1 legacy AC, V2 hybrid 800V DC sidecar (H2 2026), V3 row-level 800V DC busway (2027), V4 native 800V DC facility. Killer thesis: the hall-power cycle is a relocation of the power-conversion boundary, not a UPS replacement cycle.
Corporate structure, material contracts, change-of-control provisions, non-compete enforceability, IP filings and freedom-to-operate, litigation exposure. Where the deal thesis meets the paper record.
The workstream that tests whether the target's people, culture, and systems can execute what the other workstreams describe. Where post-close value destruction most often begins.
Third stage of Grid-to-Chip. P3.1 site power transformer (HV to MV, 48-60+ mo lead times), P3.2 MV distribution, P3.3 hall conversion (SST vs conventional), P3.4 hall interface. 800V DC changes where conversion happens; SSTs sit at the intersection.
Second stage of the Grid-to-Chip framework. P2 as grid access globally. IEA 2.5+ TW queue worldwide. Five regime archetypes: ISO/RTO, VIU, TSO/DSO, state allocation, hybrid infrastructure. Three sub-problems. US deepest case study; UK, EU, APAC, MENA.
The first stage of the Grid-to-Chip framework. P1 is a contract, not a machine. Three-tier vendor taxonomy, 2024-2026 hyperscaler comps, per-tier scorecards with worked aggregates, falsification triggers, watch calendar. Sequencing beats archetype selection.
A reference underwriting of DG Matrix, the first commercially available multi-port solid-state transformer. Interport product, NC State FREEDM Center technology provenance, Nvidia MGX ecosystem qualification (June 17, 2026), $60M Series A led by Engine Ventures with ABB and Mitsubishi Heavy Industr