What Ferric is worth after ADI paid $1.5 billion for Empower

01The thesis

The history of AI power delivery is a history of shrinking the distance between the converter and the transistor. Integrated voltage regulators are the point at which that distance becomes economically consequential.

Board-level voltage regulator modules deliver current to a processor across inches of PCB copper. Vertical power delivery cuts the distance to millimetres by routing current through the board directly beneath the die. Package-integrated voltage regulators move the last conversion stage inside the processor package itself. On-die integrated regulators put the switching silicon on the compute die.

Every step shortens the current path. Every step reduces the losses and parasitics that limit how much current a processor socket can accept. Every step also increases the cost, the packaging complexity, and the technical difficulty of the underlying silicon. The industry historically stopped at board-level VRM because the economics favoured it. AI accelerator scaling changed the economics.

IVR is parasitic management first, miniaturisation second. Current density at the compute die has risen faster than the ability of PCB copper to accommodate it without unacceptable I²R loss, without unacceptable voltage droop under fast load transients, and without exhausting the socket real estate available for power pins. The architectural pressure runs toward progressively shortening the electrical path between conversion and the transistor. Multiple topologies can coexist within the same design, and each stage of AI accelerator scaling favours further shortening rather than a single winning architecture.

The commercial marker that priced the category was Analog Devices acquiring Empower Semiconductor for $1.5 billion in cash. Announced May 19 2026, completed July 7 2026 (ADI completion press release). Ferric is the standalone challenger that remains after ADI's move. Marvell is the customer both companies have publicly targeted for design wins in custom XPU platforms. This piece works through the physics that forces IVR into existence, the architectural taxonomy that separates the credible approaches, the commercial map of who is competing where, and what the ADI-Empower comp implies for Ferric's standalone position and for the next transaction in the category.

02The physics of AI-scale power delivery

Four physical constraints force voltage regulation toward the compute die.

Wall 1: conduction loss. Power dissipated in a conductor scales with the square of the current. At 3,000 A, every microohm of path resistance dissipates 9 W. Fifty microohms dissipates 450 W. One hundred microohms dissipates 900 W. Delivering 3,000 A across even a few inches of PCB trace at practical trace widths therefore dissipates hundreds of watts as heat in the board itself. The heat competes with the compute die for thermal budget, degrades PCB reliability, and requires additional cooling investment.

Wall 2: transient response. AI accelerator workloads impose fast load transients. The power delivery network has to respond to rapid changes in current demand within nanoseconds without unacceptable voltage droop, regardless of the underlying workload frequency. Distance between the regulator and the die multiplies with trace inductance and di/dt to set the loop response speed. Shorter distance means faster response and tighter regulation.

Wall 3: physical routing. Getting 3,000 amperes into a BGA-style socket requires hundreds of dedicated power pins. Each pin displaces socket real estate that could carry signal or memory bandwidth. Below a certain current density per pin, the socket runs out of physical space for the power delivery the compute die needs.

Wall 4: thermal coupling. Once the voltage regulator moves into the package, its conduction and switching losses become part of the same thermal envelope as the compute die. The system now has to remove more heat from a smaller area. Package thermal design becomes a co-optimisation problem across the regulator and the compute silicon.

Each wall can become binding on its own. Together they create increasing pressure to place regulation closer to the load, in the specific sense that shorter current paths reduce I²R, reduce parasitic inductance, and free up socket area, at the cost of harder thermal management.

Provenance convention. Load-bearing analytical claims below are tagged P for Public (a directly sourced disclosure), D for Derived (calculated from public inputs), and I for Interpretation (analytical judgment). The convention runs consistently across every P/D/I tag in this piece.

P: H100 (Hopper, single monolithic GH100 die on TSMC 4N) draws 700 W per package. B200 (Blackwell, two dies bridged by NV-HBI on TSMC 4NP) draws 1,000-1,200 W per package. GB200 Superchip (2× B200 packages + 1× Grace CPU on a single module) draws ~2,700 W per module. Rubin and Rubin Ultra target higher still; per-package figures are not fully public (Semiconductor Engineering on AI power delivery). D: On the B200's dual-die layout, each compute tile carries roughly 500-600 W. At typical core voltages (0.75-0.85 V), core-rail current runs 800-1,100 A per compute die and 1,500-2,500 A per dual-die package. I: Board-level regulator architectures struggle economically once package currents exceed roughly 2,000 A, because I²R and transient-response penalties dominate. That pushes the architectural transition described below.

03The canonical architecture taxonomy

The industry uses "IVR" as shorthand for multiple different architectural approaches. The five architectures below cover the space.

Architecture	Regulator location	Current path from regulator to die	Primary advantage	Primary constraint
Board VRM	Motherboard	PCB traces + socket + package	Mature, low unit cost, easy servicing	Parasitic loss and inductance dominate above ~500 A per socket
Vertical power delivery (VPD)	PCB underside directly beneath socket	Vertical vias through PCB + package	Shortest board-level path; keeps discrete components	PCB via density and package co-design complexity
Package-integrated IVR (PIVR)	Inside processor package (substrate or interposer)	Package substrate routing	Very high current density; fast transient response	Package thermal envelope and yield complexity
Substrate-integrated IVR (SIVR)	Cavity within package substrate directly beneath die	Substrate vias inside cavity	Sub-millimetre distance; supports on-package multi-rail	Advanced substrate yield; CTE mismatch stress
On-die integrated IVR	On the compute die itself	Zero external routing	Minimum parasitics; per-domain fine regulation	Die area consumption; thermal hotspot; process co-design

These architectures are not necessarily competitors. A single accelerator design can combine multiple approaches at different stages. A hyperscale ASIC might use vertical power delivery for the 1.8 V intermediate rail, package-integrated IVR for the primary core rail, and on-die IVR for per-domain fine regulation. The commercial question for a merchant IVR vendor is which architecture the design wins consolidate around, and whether one architecture displaces the others across most sockets.

Historical guidance suggests architectures rarely collapse to a single winner. Server power delivery has run parallel board VRM, LDO, and captive regulator approaches for two decades. What changes with AI accelerator scaling is that the board VRM only architecture has become insufficient on its own, which opens the merchant IVR opportunity for the first time at commercial volume.

04The two-stage PDN reality

IVR does not convert 48 V directly to a sub-volt core rail. The duty-cycle penalty makes single-stage 48 V-to-0.8 V conversion physically impractical. The duty-cycle penalty of a single conversion stage from 48 V to 0.8 V produces impractical efficiency and control-loop performance. Actual AI accelerator power delivery uses a two-stage network.

Stage 1: rack DC to intermediate bus. 48 V or 54 V input from the rack power shelf (or 800 V DC bus in newer architectures) steps down to an intermediate voltage of 1.8 V to 2.0 V via a switched-capacitor converter or LLC resonant topology. Stage 1 conversion happens on the motherboard or on an intermediate power daughtercard. Vicor's BCM / VTM product line targets this stage. Navitas' 800 V-to-6 V direct-conversion power board (in the Nvidia MGX ecosystem) collapses the front-end further (Anthropic-adjacent context on 800 V DC in the wide-bandgap stack).

Stage 2: intermediate bus to core rail. The 1.8 V to 2.0 V intermediate rail steps down to the 0.7 V to 1.0 V core rail at 2,000 to 5,000 A. This is the last-millimetre stage. This is where IVR competes.

The two-stage separation matters because it clarifies who competes with whom. Empower and Ferric compete for the Stage 2 socket. They do not compete directly with Vicor or Navitas at Stage 1, though the architectural evolution of Stage 1 (particularly the direct 800 V to 6 V collapse in Navitas' Nvidia MGX product) affects the current level and voltage margin that Stage 2 has to accept as input. If Stage 1 delivers a lower intermediate voltage cleanly, Stage 2 gets an easier design target. If Stage 1 remains at higher voltages, Stage 2 has to work harder.

The two-stage PDN also explains why merchant IVR vendors cannot displace merchant intermediate-bus vendors and vice versa. Different physics, different thermal envelopes, different customer buying processes. This is the point most easily misread by investors looking at the category from outside.

05The historical proof: Intel FIVR

Intel's fourth-generation Core microprocessor family (Haswell, 2013) shipped the first at-scale on-die integrated voltage regulator. FIVR (Fully Integrated Voltage Regulator) ran multi-phase buck regulators at 140 MHz on the 22 nm processor die, used non-magnetic package trace inductors, and placed MIM capacitors on-die (Intel FIVR technical documentation, PSMA presentation).

The technology proved the physical concept. Multi-phase high-frequency regulation could work on-die with integrated passives. The concept was not the problem.

Intel removed FIVR from Skylake (2015) and Kaby Lake (2016) after discovering it was inefficient for both high-TDP processors under light workloads and low-TDP processors under heavy workloads. The technology returned partially in specific product lines starting Ice Lake but never became the dominant architecture Intel had originally projected.

FIVR failed to win in 2015 on economics. The physics worked. The board-level VRM architecture delivered adequate performance at lower unit cost for the currents in play at the time. Haswell client sockets pulled under 120 A. Haswell-EP server sockets peaked around 190 A. Consuming roughly 10% of die area on a sub-$500 processor to displace a few dollars of board-level passives and DrMOS destroyed gross margin. The math did not work.

AI accelerator scaling changed every input to that calculation. Core-rail currents jumped from Haswell's roughly 120-190 A range to 1,500-3,000 A per Blackwell-class package. I²R loss across the socket-and-board path scales quadratically with current, so the 5-10 W of parasitic loss at 100 A becomes 50-120 W at 2,000 A. The liquid-cooling envelope on modern accelerators cannot absorb that thermal budget without throttling clocks. The cost side moved further. The relevant denominator is packaged accelerator ASP. A TSMC 4NP compute die still runs roughly $400-450; a Blackwell-class packaged accelerator sells in the $30,000-40,000 range, with HBM stacks and CoWoS packaging as the dominant cost drivers. Spending a few square millimetres of silicon to recover 50-100 W of thermal headroom is a rounding-error trade at those unit prices.

P: Intel FIVR shipped on Haswell (22 nm, 2013) at 80-140 A per socket, withdrawn after Skylake / Kaby Lake (Intel Pentium Silver datasheet). D: Regulator area penalty on a $500 CPU running 100 A rails consumed too much gross margin; the physics was proven, the economics was not. I: At 2,000 A core rails and $30k+ package ASPs, the same area penalty is trivial relative to the recovered thermal margin and package routing congestion relief.

06The technology stack: what IVR actually contains

An integrated voltage regulator combines five components that historically shipped as separate discrete parts.

Switching devices. The power transistors that chop the input voltage at high frequency. Historically silicon LDMOS. Modern IVRs use finFET-integrated silicon or CMOS-compatible processes. Some approaches use GaN low-voltage devices for higher switching frequency.

Controller. The digital or mixed-signal logic that generates the switching pattern and closes the voltage regulation loop. On-chip controllers with fast ADCs enable the multi-hundred-MHz control loop that in-package IVR requires.

Inductors. The energy storage element that smooths the switched voltage into a stable DC output. Physically the hardest component to shrink into a package. Two divergent approaches exist: package-integrated air-core or ferrite-alloy inductors, and thin-film ferromagnetic inductors deposited on the CMOS wafer. The architectural implications of the split are covered in § 07.

Capacitors. Input and output capacitance for high-frequency filtering and load-transient support. Modern integrated silicon capacitors (ECAP) replace bulky external MLCCs; competing architectures split capacitance between the regulator die and the compute-die substrate differently.

Package and substrate. The physical container. Modern PIVR relies on advanced substrate technology, chiplet integration, or interposer-based approaches. TSMC's InFO and CoWoS are the two most-productised advanced package platforms hosting IVR silicon.

The technology stack decomposition matters because it clarifies where value accrues. In the merchant IVR category, the winning vendor owns the switching-plus-controller silicon design, has a differentiated inductor solution, and can qualify the package integration with a specific foundry or OSAT partner. Individual components (silicon capacitors, package substrate) are less defensible in isolation. The moat is the integration.

07The magnetics and materials split: Empower vs Ferric

The most important technical distinction between Empower and Ferric is how each vendor handles the inductor problem. Ferric's moat is thin-film magnetic-core micro-inductors deposited directly on the silicon wafer during the CMOS process. Empower's moat is high-frequency FinFast finFET switching paired with integrated silicon capacitors (ECAP) that replace external MLCCs. This is where their architectural bets diverge, and it is the single sharpest technical fork in the merchant IVR field today.

Ferric's approach: thin-film ferromagnetic inductors on CMOS. Ferric's core technology is a proprietary process for depositing thin-film ferromagnetic material directly on silicon wafers, integrated with standard CMOS transistor and interconnect layers. The result is a very high inductance-density micro-inductor built into the same die as the regulator silicon. This approach eliminates the need for discrete or package-mounted inductors and enables a form factor where the entire converter (transistors, capacitors, inductor) fits inside a single die.

The material science is the defensible piece. Ferric CEO Noah Sturcken established the thin-film magnetic technology through doctoral research at Columbia, and the company has extended the process across multiple TSMC nodes since 2019 (Ferric technology page). The flagship Fe1766 IVR delivers 160 A from 35.5 mm² of silicon with the integrated inductor, at approximately 93% efficiency, and supports scalable multi-device operation (Ferric Fe1766 launch, August 2025).

Empower's approach: FinFast finFET + integrated silicon capacitors + external magnetics minimised. Empower's FinFast switching architecture uses finFET transistors to enable very high switching frequencies (into the low hundreds of MHz), which shrinks the passive components. The company complements FinFast with proprietary integrated silicon capacitors (ECAP) that replace bulky external multi-layer ceramic capacitors. Empower's magnetics approach is package-integrated rather than on-die, using very small ferrite-alloy or air-core inductors sized for the FinFast switching frequency.

The two philosophies represent different bets on what is defensible. Ferric bets that magnetic materials integration is the moat because switching devices become commoditised. Empower bets that switching architecture and capacitor integration are the moat because passive magnetics become commoditised.

Component	Ferric approach	Empower approach
Switching devices	CMOS-compatible integrated transistors	FinFast finFET-based, higher switching frequency
Inductor	Thin-film ferromagnetic material deposited on CMOS wafer	Package-integrated air-core or ferrite-alloy inductor
Capacitor	Integrated silicon and package capacitance	Integrated silicon capacitor (ECAP), external MLCC minimised
Switching frequency	Very high (magnetic material tolerates fast switching)	Very high (finFET tolerates fast switching)
Location	Same die as regulator silicon	Same package as regulator silicon
Foundry integration	TSMC process co-development	Multiple foundries; not exclusive to any single partner
Business model	Chip vendor + potential IP licensing to TSMC customers	Chip vendor (now inside ADI)

P: Fe1766 published specification: 160 A, 35.5 mm², 93% efficiency, integrated inductor. P: Empower FinFast + ECAP disclosed in company technical materials. D: The two architectural philosophies bet on different components as the defensible moat. I: In the medium term, both approaches can coexist because customers value different trade-offs (silicon area vs package complexity vs magnetics scalability). In the long term, one architectural bet may dominate as manufacturing yield curves diverge.

08Advanced packaging: warpage, CTE, and the thermomechanical wall

Integrating regulators into substrates or interposers introduces thermomechanical failure modes that board-level VRMs never encounter, directly gating commercial packaging yield. Manufacturing yield gates which architectures actually reach commercial ramp, so the thermomechanical constraints below define the reachable design space more than the electrical performance does.

CTE mismatch. The coefficient of thermal expansion of silicon, package substrate, solder, and copper differ by factors of 2x to 10x. Thermal cycling during processor operation stresses the interfaces. Package-integrated IVR adds another die in the same package with its own thermal signature, which increases the number of thermally-driven stress cycles and can accelerate mechanical fatigue.

Package warpage. Thin substrates warp under thermal load. Adding regulator silicon and integrated capacitors to the substrate increases mass and heat dissipation, which changes the warpage profile of the entire package. Substrate-integrated IVR (SIVR) specifically depends on cavity routing in Ajinomoto Build-up Film (ABF) substrates, where CTE mismatch during solder reflow can drive early field failures if the substrate design does not accommodate the additional die. OSATs (outsourced semiconductor assembly and test providers) qualify substrate designs against warpage limits that ultimately determine what IVR footprints can ship at volume.

CoWoS and hybrid bonding integration. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) advanced package platform hosts the majority of high-end AI accelerator designs. Integrating a discrete IVR die alongside the compute die and HBM stacks in the same CoWoS package requires TSMC-side qualification of the additional die, its thermal profile, and its impact on interposer routing. Hybrid bonding, the next-generation stacking approach, has even tighter yield and thermal tolerance constraints.

Yield economics. Every additional die in an advanced package multiplies the joint yield calculation. If the IVR die yields 95% and the compute die yields 90%, the joint yield of the package under an independence assumption is 85.5%, which is lower than either die alone. Real package yield is more complicated because assembly, known-good-die screening, redundancy, binning, and correlated defect modes alter the arithmetic. The direction of the effect (joint yield is lower than either component yield) holds regardless. Package-level yield loss is expensive at $5,000+ packaged accelerator COGS. IVR vendors that produce silicon with genuinely high yield have a cost-of-goods advantage that compounds with volume.

The IVR contest runs across silicon, package, magnetics, and qualification together. Any vendor missing one of those layers loses. Vendors that can co-qualify their design with TSMC, Samsung Foundry, or an OSAT partner at scale have a moat that a pure-silicon-IP vendor cannot match. Ferric's decade-long TSMC integration and Empower's finFET-based silicon designed for advanced package integration both reflect this reality.

09The commercial ecosystem: who plays where

Four categories of vendors are chasing the merchant IVR opportunity from different starting points.

Category A: pure-play merchant IVR vendors. Empower (now ADI) and Ferric. The two companies specifically discussed in this piece. Both have published product with named design wins targeting AI accelerator sockets.

Category B: merchant multi-phase VRM incumbents. Monolithic Power Systems (NASDAQ: MPWR), Renesas, Infineon (via Cypress and IR heritage), Texas Instruments, Alpha & Omega Semiconductor, STMicroelectronics. These companies dominate the board-level VRM socket for CPUs and mid-range GPUs. Each has a published or announced roadmap toward higher-density integrated modules but none has demonstrated a shipping in-package IVR at the specification Empower and Ferric deliver.

Category C: analog majors with silicon-power heritage. Analog Devices (post-Empower). NXP, Renesas, and Onsemi each have power-management portfolios that include silicon-integrated regulators at lower density and lower switching frequency. Any of these could plausibly acquire a Ferric-analog to fill the ADI-Empower gap.

Category D: foundry-integrated and captive IVR programs. TSMC via the Ferric partnership. Intel Foundry Services with legacy FIVR IP. Samsung Foundry with published research on integrated voltage regulators. Hyperscaler captive silicon programs (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) with internal power delivery teams that could either license merchant IVR IP or develop captive equivalents.

A useful frame for the competitive field uses three orthogonal dimensions: switching device (silicon vs GaN), regulator location (board vs vertical vs package vs die), and business model (merchant chip vs IP license vs captive). Empower and Ferric both bet silicon device + package/die location + merchant chip (Empower) or merchant chip plus IP license (Ferric). GaN pure-plays are betting GaN device + intermediate-bus location + merchant chip. Captive programs are betting silicon or GaN + on-die location + captive.

Architecture family	Named vendors	Switching frequency	Total area (indicative)	PDN resistance (indicative)	Packaging complexity
Monolithic on-die IVR (FIVR family)	Intel FIVR heritage; hyperscaler captive R&D	~140 MHz (historical Intel FIVR)	Consumes die area	Very low (~µΩ, on-die routing)	Requires processor die redesign
Package-integrated IVR	Empower (ADI), Ferric	100-200+ MHz	Package footprint 30-40 mm² per unit	Low (~10s of µΩ, package routing)	Advanced substrate integration required
Discrete vertical power delivery	Infineon, MPS, Vicor, Renesas roadmap	1-10 MHz	PCB underside footprint	Moderate (~100s of µΩ, via array plus package)	PCB and package co-design; standard OSAT

Note: PDN resistance and area values are indicative rather than published benchmarks; specific comparisons depend on the customer processor and package.

10Empower Semiconductor and the ADI acquisition

Empower was founded in 2014 by Tim Phillips, a Silicon Valley power semiconductor veteran with prior roles at International Rectifier and Volterra Semiconductor. The company's core intellectual property is the FinFast switching architecture combined with integrated silicon capacitor technology.

Capital history.

• Series A through C: early ARPA-E anchor plus VC syndicate through 2015-2022
• Series C1: $45 million (company release, 2024)
• Series D: $140+ million led by Fidelity Management & Research, September 2025 (Electronic Design coverage)
• Total private capital raised: approximately $236 million
• Acquired by Analog Devices for $1.5 billion in cash. Announced May 19 2026 (ADI announcement release). Completed July 7 2026 (ADI completion release).

Named commercial engagement. The confirmed public design win is Marvell's custom XPU platform; the SKU-level allocation and hyperscaler pull-through are analysed in § 12.

Strategic rationale for ADI. P: ADI's own language positions Empower as "a leading strategic, system-level grid-to-core power partner across the entire AI ecosystem, expanding ADI's total addressable market and capabilities in AI compute power delivery." ADI identifies IVR and silicon capacitor technology as the specific strategic additions. D: ADI's existing power portfolio (Linear Technology, Maxim, Silergy heritage) covers silicon-integrated power management at conventional current densities. It did not include package-integrated IVR at the specification Empower delivers. I: The transaction gives ADI a defensible position in the merchant IVR socket that would have taken multiple years and multiple hundreds of millions of R&D dollars to build internally. The strategic urgency is Marvell's XPU pipeline and adjacent hyperscaler custom silicon programs going into 2027-2028 designs.

Deal economics. At $1.5 billion in cash on approximately $236 million total private capital, the transaction priced Empower at roughly 6.4x total invested capital across a decade of build. The comparison anchor comes from inside the IVR and high-density DC-DC category rather than from solid-state transformers. Monolithic Power Systems acquired Volterra Semiconductor in September 2013 for approximately $605 million (~6x trailing revenue on Volterra's roughly $100 million revenue base). Volterra was the closest architectural predecessor to today's on-package IVR players: a high-integration DC-DC converter company selling into CPU/GPU voltage-regulator sockets, bought by a strategic scale player moving up the power-density integration stack. MPS's own equity ramp since (from ~$5 billion market cap in 2020 to ~$40 billion by 2026, driven substantially by AI-server power-management demand) provides the public-market read-through on the same category thesis. Empower's private valuation implied by its 2023 Series C round runs well below the MPS-Volterra print in absolute dollars but at broadly similar revenue multiples, telling you the IVR-category pure-plays remain earlier-stage than their design-in traction (Marvell for Ferric on the confirmed public record, AMD MI400 and Intel Foveros reported for Empower) would suggest at full ramp. The category re-prices when hyperscaler and accelerator-OEM standardisation locks in through 2027-2028.

11Ferric as the strategic comparator

Ferric was founded around 2010 by Noah Sturcken, a Columbia University PhD whose doctoral research established the foundation for the company's thin-film magnetic technology. Headquartered in New York City, geographically distinct from the Silicon Valley cluster where most competing IVR IP developers sit.

Capital history.

• Multiple early rounds anchored on non-dilutive government funding: DARPA, US Air Force, US Department of Defense, US Department of Energy
• Series C: $32.11 million (December 2, 2024)
• Total private capital raised to date: approximately $41.1 million (CB Insights financials)
• Independent as of September 2026; no acquisition process publicly disclosed

Technology position. The Fe1766 flagship IVR delivers 160 A from 35.5 mm² of silicon with integrated thin-film ferromagnetic inductors, at approximately 93% efficiency, targeting in-package placement adjacent to the compute die. Ferric's architecture is built around its long-standing TSMC manufacturing and integration relationship, which dates back to public co-presentations in 2019.

Named commercial engagement. The confirmed public design engagement is Marvell (announced June 17 2025), roughly nine months ahead of Empower's own Marvell announcement. The sourcing-split question and its implications are handled in § 12.

IP position. Ferric holds patents around thin-film magnetic inductor integration with CMOS, developed through Sturcken's Columbia research and expanded with DARPA-funded work across more than a decade. The specific granted-versus-pending count varies by source. Ferric's patent portfolio and long-running TSMC integration appear central to its differentiation. The extent of exclusivity and the availability of equivalent design-arounds at equivalent performance are not publicly disclosed.

P: Ferric has raised approximately $41.1M in total private capital, most recently a $32M Series C round. P: Fe1766 published specification and Marvell collaboration announced June 17 2025. D: The TSMC integration is architecturally central to Ferric's business model. The exact commercial terms and any exclusivity provisions are not publicly disclosed. I: The combination of a decade-long TSMC integration, a shipping product with named design wins, and $41M total capital raised makes Ferric the most credible independent IVR play in the market post-ADI-Empower.

12The Marvell signal: the first battleground is custom silicon

The most-underweighted observation in the merchant IVR field is that both Empower and Ferric have publicly-disclosed Marvell relationships, not Nvidia. Marvell itself has publicly described its package-integrated voltage regulator (PIVR) strategy as moving from board-level power delivery toward tightly coupled integrated silicon and passives, targeting 2x current density and up to 85% lower transmission losses for the final conversion stage (Marvell PIVR announcement).

Marvell is the second-tier merchant player in the AI accelerator socket, positioned behind Nvidia's reference designs. Its custom XPU program serves hyperscaler ASIC customers. The Marvell design cycle for a customer accelerator involves specifying the power delivery architecture two to three years before shipment, which places 2026 design decisions inside the 2028-2029 accelerator ship windows.

The Marvell test. The first observable merchant IVR battleground is custom silicon. Nvidia's own reference design keeps the architecture captive.

Marvell has publicly signalled the architectural move toward PIVR. Both Empower (now ADI) and Ferric have announced Marvell collaborations. Hyperscaler ASIC programs sourced through Marvell will therefore be the earliest visible market for merchant IVR silicon at scale.

Nvidia's own accelerator power delivery architecture is captive to Nvidia's design process and is less observable in public filings. Watch Marvell first.

The falsifier. If Marvell ultimately internalises its power architecture into its own silicon and package stack, the addressable merchant-IVR market is materially smaller than the current vendor narrative implies.

13IVR versus GaN: substitution or complement

The IVR category as defined so far assumes silicon (CMOS) as the switching device. A parallel bet uses gallium nitride (GaN) low-voltage devices instead. GaN offers higher switching frequency for the same conduction loss than silicon, which enables smaller passive components and higher power density per package.

Four GaN vendors matter for the AI accelerator socket.

• EPC (Efficient Power Conversion). US, founded 2007. GaN enhancement-mode pioneer. Ships 15V-100V GaN FETs for point-of-load applications. Not a full IVR product vendor; sells the switching device to VRM and POL module makers.
• Innoscience (2577.HK). Chinese, listed. Dominant merchant GaN vendor with 8-inch GaN-on-silicon platform. Ships 100V GaN FETs for AI rack power delivery. Covered in depth in the wide-bandgap-stack essay.
• Navitas Semiconductor (NASDAQ: NVTS). US, listed. GaN pure-play with 100V-class devices and specific Nvidia MGX ecosystem position via the 800V-to-6V direct-conversion power delivery board.
• Cambridge GaN Devices. UK, university spin-out. Novel enhancement-mode GaN transistor structure at very high switching frequency.

The strategic relationship between IVR (silicon-based) and GaN low-voltage devices is either substitution or complement. The critical question:

Can GaN economically deliver the required current at the required voltage and thermal density close enough to the die to eliminate the need for silicon IVR?

If the answer is no through 2028, GaN devices remain better at the intermediate bus (48V to 6V, or 800V to 6V) while silicon-based IVR remains better at the final core rail (6V to 0.7V at thousands of amperes). Both coexist.

If the answer becomes yes by 2028-2029, GaN devices displace silicon IVR at the core rail, and the merchant silicon-IVR opportunity could contract sharply as the switching function migrates into an alternative architecture.

The current technical read favours coexistence through at least 2028. GaN thermal performance and yield at the very low-voltage, very high-current end are not yet at parity with integrated silicon. The Innoscience roadmap and EPC low-voltage FET scaling both point toward continued GaN dominance at the intermediate stage, not at the core rail.

14The $1.5B reverse-underwrite

Clearing a 15% IRR on ADI's $1.5 billion cash purchase of Empower requires a rigorous reverse-underwrite. What operating performance justifies the price?

Purchase price: $1.5 billion cash. Illustrative underwriting assumptions: 15% IRR over five years, 60% gross margin at maturity, 4× forward gross-profit terminal multiple. These are the assumptions used to generate the table below. They are directional. No specific comparable transaction was used to benchmark them.

Working backwards from these assumptions produces an approximate annual gross profit that Empower needs to generate for the transaction to clear the hurdle. At 60% gross margin, the revenue required to produce that gross profit maps back to a specific annual-revenue target.

Empower annual revenue by year 5	Gross margin	Gross profit	Terminal multiple	Terminal EV	Implied IRR	Note
$100M	60%	$60M	4×	$240M	−30.8%	Fails
$300M	60%	$180M	4×	$720M	−13.7%	Fails
$500M	60%	$300M	4×	$1.20B	−4.4%	Below hurdle
$750M	60%	$450M	4×	$1.80B	+3.7%	Positive; below hurdle
$1.0B	60%	$600M	4×	$2.40B	+9.9%	Approaches hurdle
$1.5B	60%	$900M	4×	$3.60B	+19.1%	Clears 15% hurdle

Margin realism. A flat 60% gross margin is a comfort assumption. Realistic merchant IVR margins depend on how much of the value chain the vendor controls against its customers. Monolithic Power operated at approximately 55-58% gross margin at the time of the Volterra acquisition. Silicon Labs sustained 55-60% at scale. Cirrus Logic dropped below 45% under Apple pricing concentration. Marvell as the primary Empower design-win customer represents similar concentration risk. Packaging yield drag, TSMC substrate cost pass-through, and hyperscaler pricing power all bias the number downward through the first two to three years of ramp. The heatmap below extends the reverse-underwrite across a 40% to 70% gross-margin band to show where the hurdle actually clears.

Terminal-multiple sensitivity. The heatmap holds terminal multiple at 4x forward gross profit. At 3x, subtract roughly 5 percentage points of IRR from every cell; at 5x, add roughly 4 percentage points. The 15% hurdle contour shifts left and right accordingly. Any Empower valuation model that assumes both a rich terminal multiple AND a rich sustained gross margin AND aggressive revenue ramp compounds three optimistic assumptions inside a single model.

Note: IRR calculated as (Terminal EV / $1.5B)^(1/5) − 1. The table uses a 4× forward gross-profit terminal multiple. At 5×, the 15% hurdle clears at approximately $1.0 billion revenue instead of $1.5 billion. Actual ADI accounting for Empower will include strategic-value premium, revenue synergies with ADI's existing power portfolio, and cost synergies that reduce the standalone-revenue hurdle. The table exists to give directional guidance rather than a valuation forecast.

The implied annual revenue target for the deal to clear a 15% IRR hurdle at year five, absent strategic-value premium, is roughly $1.0 to $1.5 billion at 4× to 5× terminal gross-profit multiples. Empower's revenue at the time of the acquisition announcement was not disclosed. Reasonable estimates place it well below this range, perhaps under $100 million annual revenue. Getting from that base to the required target within five years requires annual-revenue growth of 40% to 80% compounded across the acquisition period. That is a demanding growth curve. Several semiconductor products have compounded at that rate through an inflection window when the strategic moat is strong.

Bottom line: ADI paid a large absolute price for a currently-small asset positioned at what is projected to be a critical bottleneck. The Empower valuation supports itself only if merchant IVR volume ramps at 30-40% CAGR through 2028, matching the pace the current Nvidia design-in traction implies. Two failure modes break the case: a 2-year migration slippage that pushes revenue right, or GaN substitution collapsing the merchant IVR category before Empower's volume ramp compounds.

15Ferric valuation framework

Analytical valuation scenarios, not market estimates. Same discipline as Section 16.

For the private-market read on Ferric, the anchor is the $1.5 billion ADI-Empower comp adjusted for three variables Ferric-specific.

Variable 1: demonstrated silicon revenue. Empower reached ADI's acquisition on approximately $236 million total capital raised and an inferred low-triple-digit-million-annualised revenue trajectory. Ferric has raised approximately $41 million total and its revenue is not publicly disclosed. Any acquirer or IPO underwriter will discount Ferric's valuation on the revenue-scale gap unless a matching Series D round is closed at scale first.

Variable 2: design-win conversion. Empower's Marvell collaboration and any Nvidia-adjacent design wins carry strategic weight. Ferric's Marvell collaboration is public but the SKU-level status is less clear. Additional named design wins (a second hyperscaler ASIC program, a Nvidia MGX component vendor confirming Ferric silicon, a European automotive-adjacent design) would each reprice the standalone position.

Variable 3: IP licensing economics. This is the dimension where Ferric can potentially outrun Empower's business model. The IP-multiple case depends on Ferric demonstrating a materially different revenue architecture. Without royalty economics actually materialising, only the semiconductor-chip multiple applies. The TSMC integration relationship provides Ferric with a path to license inductor libraries and IVR IP to TSMC's own customers for direct on-die integration. If Ferric captures royalty revenue on hyperscaler custom silicon programs that embed Ferric IP on their own compute die, the revenue-multiple valuation approach for Ferric shifts from a chip-vendor model (5-10x revenue) to a semiconductor IP model (15-25x revenue). This is the bull-case value driver.

Valuation for Ferric therefore evolves with the evidence that lands over the next twelve to eighteen months. Rather than a single price target, the framework maps observable evidence to a re-rating trigger.

Evidence achieved	Interpretation for standalone Ferric value
Fe1766 technology demonstration only	Interesting technology; lower valuation bound holds
Multiple qualified production designs (beyond Marvell)	Category-formation evidence; first re-rating trigger
Marvell production deployment at SKU level	Commercial validation; second re-rating trigger
Hyperscaler XPU design-in named publicly	Strategic-scarcity premium applies
TSMC embedded/licensing revenue disclosed	Semiconductor-IP category applies; multiple expands to 15-25× revenue

Against that evidence backdrop, three brackets:

Bracket	Positioning	Implied valuation	Trigger
Bear (primarily silicon business)	Ferric captures a niche merchant position but no material IP licensing	~$400-700M	Series D at $300-500M pre-money, or acquisition by a smaller analog major (Renesas, Onsemi) at that range
Base (silicon + strategic design wins)	Ferric wins multiple named design wins alongside Empower/ADI in Marvell and hyperscaler custom silicon	~$1.0-1.8B	Series D at $800M-$1.2B pre-money, or acquisition at $1.5-1.8B by a comparable acquirer
Bull (demonstrated IP licensing economics)	Ferric locks in hyperscaler on-die IP licensing at scale, semiconductor IP business model applies	~$2.5-4.0B	Public disclosure of a specific hyperscaler on-die IVR program using Ferric IP, or an IPO priced on IP-multiple economics

Strategic endgame for Ferric. If the company is acquired rather than IPOing, five buyer candidates plausibly compete.

• Analog Devices: unlikely, already has Empower
• Marvell: could vertically integrate Ferric to lock in package-integrated power for the XPU platform
• Qualcomm: has a stated AI accelerator ambition and no in-house IVR at Ferric-class specification
• Monolithic Power Systems (MPS): natural incumbent play; would use Ferric to leapfrog Empower/ADI at the integrated end
• Texas Instruments: same rationale as MPS with a larger balance sheet
• A hyperscaler direct acquirer (Google, Meta, Amazon): less likely due to antitrust and neutrality concerns; possible as a defensive supply-chain acquisition

The Marvell and Qualcomm cases are the most strategically-loaded because they represent a captive-silicon buy that removes Ferric from the merchant market entirely. MPS and TI cases keep Ferric merchant but under a larger commercial channel.

16Scenarios through 2029: analytical calibration only

The following three scenarios are analytical calibration scenarios. They are not market forecasts. Their purpose is to establish what observable evidence would distinguish competing outcomes for the merchant IVR category. Each scenario has a defining trigger that would be visible in publicly-available disclosures.

Scenario A: ADI-Empower dominates. ADI leverages its channel and post-acquisition integration to lock in the majority of merchant IVR design wins across Marvell XPU pipeline, Nvidia-adjacent ASIC programs, and hyperscaler custom silicon. Ferric captures niche defence-adjacent design wins and specific TSMC licensing engagements but does not scale to the merchant-vendor position. Ferric eventually acquired at a discount to the Empower comp (~$400-800M range) by a smaller analog major or foundry partner.

• Trigger: ADI Q4 2026 or Q1 2027 disclosures show Empower design-win capture rate above 60% of new custom XPU programs.

Scenario B: Two-vendor merchant ecosystem. Marvell continues to source from both Empower/ADI and Ferric at the SKU level. Nvidia adopts merchant IVR for ASIC-adjacent products and picks Ferric for the TSMC-integrated path and Empower for a different SKU family. Hyperscaler custom silicon splits between the two vendors along business relationship lines. Ferric raises a Series D at scale or is acquired at the Empower comp (~$1.5-1.8B) by an incumbent seeking to match the ADI position.

• Trigger: Marvell publicly discloses multi-source IVR sourcing for its next-generation XPU program. Concurrently, Ferric closes a Series D above $100 million at a $1B+ pre-money valuation.

Scenario C: On-die IVR takes the socket. AI accelerator scaling forces on-die IVR back into the dominant architecture position that Intel FIVR occupied briefly with Haswell. Ferric's TSMC-integrated IP licensing captures royalties from hyperscaler and Nvidia designs that embed IVR IP directly on the compute die. Empower/ADI captures the in-package IVR segment but grows more slowly than in Scenario A because in-package becomes a subset of total IVR opportunity. Ferric IPOs at $3-5 billion on IP-licensing revenue multiples, or acquired at $2-3B+ by TSMC directly.

• Trigger: Any hyperscaler (Google, Amazon, Meta) publicly discloses on-die IVR integration in a next-generation ASIC, OR TSMC discloses a broadening of the Ferric IP licensing program.

Each scenario is internally consistent. The evidence that would tip the read is public and visible on standard tracking cadence (quarterly earnings, hyperscaler press releases, Series D announcements, patent filings).

17Risk framework: what breaks and what remains open

Two distinct risk categories deserve explicit treatment. The first is what a merchant IVR win does not solve, so the buyer of the thesis knows the residual problems the category leaves in place. The second is what would falsify the thesis outright, so the disciplined investor knows which signals would collapse the merchant IVR opportunity.

Residuals: what IVR does not solve. The migration moves the power-delivery problem from the PCB into the package. It does not eliminate the problem. The following remain open even in the winning scenario.

• Package thermal dissipation. The regulator's own switching and conduction losses now sit inside the compute-die thermal envelope. Package cooling has to absorb both.
• Magnetic component losses. Even integrated magnetics dissipate real power at hundreds of amperes and hundreds of MHz. Better switching does not eliminate magnetic loss; it changes where the loss is dissipated.
• Package warpage and CTE mismatch. Advanced substrates with cavity routing add mechanical stress modes that PCB-level VRM never encountered.
• Substrate routing complexity. Additional die in the package add signal-integrity and power-integrity constraints on the interposer or substrate.
• Manufacturing yield. Every added die multiplies the joint-yield calculation. IVR-integrated packages are more expensive to produce than the sum of their components.
• Qualification cycle. New package configurations require thermal, electrical, and reliability qualification before customer deployment. Time to production is measured in years.
• HBM and package interaction. The IVR die competes for interposer real estate with HBM stacks and other chiplets. Package designers face a trade-off, not a free win.
• Total system efficiency. Moving losses into the package can reduce the overall PDN loss but may increase junction temperature, which reduces sustained compute performance. The net efficiency change depends on the specific workload and cooling design.
• Economic allocation between vendors. Value migrates across the silicon-package-magnetics stack. Who captures which share of the value is a commercial negotiation rather than a technical outcome.

Read the list directionally. The scarce capability shifts from power-conversion silicon alone to co-design across silicon, magnetics, substrate, package, thermal, and qualification.

Falsifiers: what would break the thesis. Seven scenarios would collapse the merchant IVR opportunity. Any two landing together are sufficient to invalidate the underwrite.

1. GaN moves directly into the core-rail regime. If GaN low-voltage FETs achieve thermal performance and yield sufficient to serve the 0.7-1.0 V, 2,000-5,000 A core rail directly, silicon-based IVR becomes redundant. Watch Innoscience roadmap for sub-40V GaN with matching current density.
2. Advanced packaging solves parasitics without moving regulation into package/die. Novel PCB substrates, exotic interconnect materials, or new via architectures might reduce parasitic loss enough to keep board-level VRM viable at 3,000+ A. Watch materials-side announcements from PCB substrate vendors.
3. Accelerator power stops scaling. If AI training and inference workloads plateau on per-chip power draw around 1.5-2 kW, the current density that forces IVR into existence stops rising, and the marginal benefit of IVR shrinks toward zero.
4. Captive hyperscaler silicon displaces merchant IVR. If Google, Meta, Amazon, and Microsoft develop captive IVR IP inside their own ASIC programs, merchant IVR loses the hyperscaler slice of the demand. This does not eliminate the category. It could materially reduce the addressable merchant market.
5. Thermal penalties overwhelm electrical benefits. If package-integrated IVR proves to raise die junction temperature enough to reduce compute clock frequency, the net system performance benefit disappears. Watch OSAT and TSMC package-thermal disclosures.
6. Package manufacturing yield collapses. If IVR-integrated advanced packages fail to achieve competitive yield at scale (below 90% joint yield), the cost per die exceeds the cost of alternative approaches. Watch TSMC CoWoS and OSAT yield disclosures.
7. A new architecture collapses intermediate conversion stages entirely. Direct 800 V to core-rail conversion via novel wide-bandgap devices, or optical power delivery, or some other radical architectural change, could bypass the IVR stage entirely. Speculative today but not impossible over a five-to-seven year horizon.

The thesis is that power density will increase faster than conventional PDNs can economically accommodate, forcing regulation into the package or onto the die. Any of the seven falsifiers above would break that specific chain, and any two together should trigger an immediate re-underwrite of the category.

18Decision rules and watch list

For the operator or system-buyer sourcing IVR. Multi-source procurement between ADI-Empower and Ferric through at least 2027 is the safe path. Both vendors cover roughly overlapping technical performance envelopes with different commercial models. Neither has demonstrated a specific technical lead beyond the other at the current shipping specification. Locking in single-source risks channel dependency for a critical component.

For the private-market investor. Ferric is the accessible IVR pure-play. The December 2024 Series C at $32 million is now roughly two years old. A Series D is plausibly within the next twelve months. Series D pricing above $500M pre-money reprices the standalone Ferric position toward the Empower comp. Any acquisition process in the next twelve to eighteen months would set the second public data point on the IVR category.

For the public-market investor. ADI is the direct listed exposure to IVR through the Empower integration. The Empower asset adds a specific but small fraction of ADI's total revenue base, so the deal itself does not move ADI stock on a quarterly basis. The signal worth tracking is the strategic story ADI tells around AI power delivery and the design-win momentum reported through 2026-2027 earnings. Watch that narrative rather than short-term Empower-specific accounting.

Watch list for Q4 2026 through 2027.

1. ADI Q4 2026 or Q1 2027 earnings, with specific attention to Empower integration commentary and any disclosed design-win momentum in AI power delivery
2. Ferric Series D announcement, if and when it occurs, and specifically the pre-money valuation
3. Marvell public commentary on custom XPU power delivery sourcing for 2027-2028 products, particularly at Marvell's investor day and industry conferences
4. Nvidia Rubin Ultra public disclosures around IVR or PIVR architecture, especially any named vendor commentary
5. TSMC technology briefing content on integrated voltage regulator ecosystem partners, especially at TSMC Technology Symposium
6. Any competing acquisition (Renesas, TI, Onsemi) that would validate the ADI-Empower precedent as category-shaping
7. Hyperscaler custom silicon programs (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) disclosing IVR or PIVR sourcing
8. GaN vendor roadmap disclosures targeting core-rail voltage/current combinations (Innoscience, Navitas, EPC quarterly updates)
9. Advanced package yield disclosures from TSMC and leading OSATs, especially any commentary on multi-die package qualification for AI accelerators

The category has one anchor comp ($1.5B), one publicly-named challenger (Ferric), one open architectural question (in-package vs on-die), and a two-to-four year window during which the merchant IVR position remains contestable. That window closes when either ADI-Empower consolidates a dominant channel position, or the on-die architecture displaces the merchant category entirely, or a falsifier lands. Ferric's outcome is one of several observable signals that will shape the read. In rough priority order, watch: actual accelerator architecture disclosures from Nvidia and hyperscalers; Marvell design-win commentary; ADI Empower-integration reporting; Ferric commercial traction and any financing round; foundry and package-integration announcements; GaN low-voltage performance milestones.

The thesis. IVR migrates the power-delivery problem from the PCB into the package. The scarce capability shifts toward co-design across silicon, magnetics, substrate, package, thermal, and qualification. Winning on regulator quality alone is insufficient. The moat is the integration.

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Canonical vocabulary

VRM (Voltage Regulator Module): board-level voltage regulator, historically the workhorse for CPU and mid-range GPU power delivery. VPD (Vertical Power Delivery): architecture where the regulator is placed on the opposite side of the PCB directly beneath the processor die, with current flowing vertically through the board. Uses discrete regulator components in a different location. PIVR (Package-Integrated Voltage Regulator): regulator silicon placed inside the processor package on the substrate or via an interposer. SIVR (Substrate-Integrated Voltage Regulator): PIVR variant where the regulator is placed inside a cavity in the package substrate directly beneath the compute die. IVR (Integrated Voltage Regulator): in this piece, the umbrella term for voltage regulation integrated into the processor package or die. Industry usage varies. Specific package implementations are PIVR and SIVR; die-level integration is on-die IVR. FIVR (Fully Integrated Voltage Regulator): historically associated with Intel's Haswell-generation on-die IVR implementation. Sometimes used generically for on-die IVR. PDN (Power Delivery Network): the full electrical path from the power source through all conversion stages to the processor die. ECAP: Empower's proprietary integrated silicon capacitor, replacing external MLCCs. FinFast: Empower's proprietary finFET-based switching architecture for very-high-frequency IVR operation. Thin-film ferromagnetic inductor: Ferric's proprietary magnetic material deposited on the CMOS wafer to build integrated inductors. CoWoS: TSMC's Chip-on-Wafer-on-Substrate advanced package platform, host to most high-end AI accelerator designs. CTE (Coefficient of Thermal Expansion): material property that determines mechanical stress at package-integration interfaces under thermal cycling. OSAT (Outsourced Semiconductor Assembly and Test): the third-party vendors that assemble and test semiconductor packages at scale. Marvell PIVR: Marvell's public strategy for package-integrated voltage regulation targeting custom XPU platforms.

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Sources cited

• ADI announcement release, May 19, 2026
• ADI completion release, July 7, 2026
• Electronic Design coverage of Empower Series D
• Empower Semiconductor Series C1 announcement
• Empower and Marvell collaboration announcement
• Marvell PIVR announcement
• Ferric Fe1766 launch, BusinessWire August 2025
• Ferric technology page
• Ferric News, including Marvell collaboration
• Ferric CB Insights financials
• Ferric Crunchbase profile
• Intel FIVR technical documentation (Pentium Silver datasheet)
• PSMA presentation on Intel FIVR package view
• Semiconductor Engineering: Power Delivery Challenges for AI Chips
• MPS-Volterra acquisition (Sep 2013 valuation anchor for IVR category)
• Wide-Bandgap Stack, adikumar.co, August 2026