The AI Semiconductor Waterfall: $34M of Silicon Per MW of Compute

00How the $34.2M per MW breaks down

Four semiconductor-bearing equipment pools share the same customer and the same reference denominator, but each has a different physical or economic demand driver. Compute silicon is architecture-driven (GPU count per MW, HBM per GPU, rack topology). Storage silicon is workload-driven (checkpoint frequency, retention policy, dataset cache depth) at prices that have risen 5× since mid-2025. Networking silicon is topology-driven (cluster scale, spine tiering, optics-per-GPU ratio). Power semiconductor content is voltage-architecture-driven (48V vs 800V DC, SiC penetration into each conversion stage). Absolute scales differ by two orders of magnitude across the four; the demand drivers, growth rates, and vendor concentrations differ across all of them.

This piece decomposes 1 MW of AI IT load into silicon dollars, layer by layer, at a specified reference architecture. Four waterfalls: compute, storage, networking, power semiconductor. Numbers grounded in vendor filings, teardowns, and management guidance. Reference case, Blackwell generation, GB200 NVL72 platform: approximately $34.2M of semiconductor-bearing equipment value per MW installed. Call the ratio itself semiconductor intensity ($/MW): the durable unit of account for AI infrastructure economics, one that survives generational chip changes.

A note on the word "silicon." The title uses "silicon" as shorthand for semiconductor-bearing equipment value. The waterfall measures equipment ASP (accelerator ASP, enterprise SSD price, optical module ASP, switch ASIC allocation, power-device content), not wafer cost, not semiconductor-company revenue, not gross profit, not free cash flow, not market capitalisation. Each of those is a separate transformation with its own capture ratio. Section 07 walks through the conversion; the "Model boundary" callout states the scope in one paragraph.

The second claim, and the more portable one. The correct economic denominator changes with whichever resource is the binding constraint. $/MW is a utility-bill view when power is scarce. $/PFLOP is a compute-capacity view when capex is scarce. GB/GPU applies when HBM allocation is scarce. $/Tbps applies when interconnect is scarce. $/kW at 800V DC applies when rack power delivery is scarce. CoWoS wafer starts apply when advanced packaging is scarce. Every AI-infrastructure investment thesis implicitly bets on which of those is the binding constraint. The waterfall answers the $/MW view; the constraint ladder converts the answer into whichever denominator matches the reader's bottleneck.

So what. Underwriting an AI-infrastructure vendor requires knowing which of the four waterfalls its revenue flows through and which denominator the market is pricing that waterfall against. Nvidia grows off a ~$23M-per-MW line priced against $/MW. Solidigm and Kioxia grow off a ~$9M-per-MW line priced against $/TB and the NAND cycle. Wolfspeed grows off a ~$300K-per-MW line priced against 800V DC adoption pace. Every basket has structural AI-infrastructure exposure; whether that translates into shareholder returns depends on capture ratio, cyclicality, ASP compression risk, and the denominator the market assigns. Current multiples already reflect scale gap, capture ratio, and denominator choice. The interesting question over the next two years is whether the vendor mix inside each waterfall shifts and whether the binding constraint moves.

01Reference architecture: what a MW contains

Five levels of AI semiconductor economics

Before decomposing the MW, one framework note. AI semiconductor economics operate across five distinct levels. Each has its own unit, its own analytical question, and its own set of vendors. Conflating them is the most common analytical error in the sector:

Same installed MW, radically different economics per company. Two vendors selling into the same AI hall can end up with entirely different revenue lines, gross margins, and multiples depending on which level of the hierarchy they occupy. Everything below is the mechanism.

Every $/MW figure in this essay resolves back to a specific rack architecture and a specific denominator. Choosing the wrong reference is how vendor claims about "content per MW" diverge by 2-3×. The baseline used throughout:

The GB200 NVL72 rack is the current-generation reference platform for hyperscale AI training. Nvidia positions it at 120 kW liquid-cooled with 72 B200 GPUs plus 36 Grace CPUs and 18 NVSwitch chips. Reference rack cost is approximately $3.0M ($2.8-3.4M range) for hyperscaler-configured units. One megawatt of IT load equals 1000/120 = 8.33 racks, containing 600 B200 GPUs. Rounded numbers (8 racks / 576 GPUs) appear elsewhere in industry commentary; this essay uses the exact normalisation to keep per-MW arithmetic clean. Read the 600-GPU figure as an economic normalisation; literal deployment configurations differ. Nobody procures 0.33 of a rack; the fractional-rack arithmetic exists to make cross-vendor and cross-architecture comparison possible on a single denominator.

What the $34M includes and excludes

The waterfall measures one-time semiconductor-bearing equipment value associated with 1 MW of installed IT load. That is a snapshot of procurement cost at reference-architecture pricing. Downstream conversions to supplier revenue, gross profit, or lifetime economic value are separate calculations covered. The boundary matters. What's inside and outside:

Boundary rule: the natural procurement unit for each layer

One consistent rule governs what counts as "semiconductor-bearing equipment" across the layers: the model captures each item at its smallest natural procurement unit when bought as a semiconductor-bearing assembly by a hyperscaler. The layers look like different scopes on first read because each is priced at its own natural procurement level: whole SSDs, whole optical modules, bundled accelerator ASP, discrete power devices. The rule and its application:

The apparent inconsistency (storage counted at whole-SSD level, power semi counted at bare-device level) resolves under the natural-procurement-unit rule. Enterprise SSDs are procured as complete drives with controller + NAND + firmware as one SKU. Power semiconductors are procured as discrete devices from Infineon / STMicro / onsemi / Wolfspeed and then integrated into PSU/SST/UPS assemblies by system vendors (Vertiv, Delta, Eaton, ABB) who add copper, iron, magnetics, and enclosure value that stays outside the semi-bearing category. Counting the whole PSU would double-count with the facility-infrastructure line already excluded from this piece. The vendor value-capture ratios (compute ~80-87%, storage ~55-65%, networking ~55-70%, power semi ~50-65%) already price this boundary correctly.

Nameplate MW vs operational draw

Two practitioner caveats on the 8.33 racks/MW figure. First, the 8.33 is arithmetic (1000 kW / 120 kW), not a real procurement quantity. Nobody buys fractional racks. The figure represents an average density across a hyperscaler fleet at Blackwell-generation 120 kW/rack. The ratio moves with each generation: Rubin Ultra pushes rack power toward 600 kW, which pulls the ratio to ~1.7 racks/MW, and post-Rubin roadmaps discuss 1 MW/rack (1 rack/MW). Any $/MW figure quoted for Blackwell is only comparable to another Blackwell $/MW figure with the same rack-density assumption; the whole waterfall recomposes on generation change. Second, NEC 80% continuous-load rules and colocation breaker sizing mean a 120 kW nameplate rack rarely draws 120 kW continuously; hyperscaler halls typically operate 80-95% of nameplate depending on workload duty cycle. The essay prices semiconductor content against nameplate MW because that is what the procurement contract sizes against; operational utilisation shifts revenue timing, not installed silicon.

Semiconductor intensity: the named metric

The denominator hierarchy. "1 MW IT load" is used throughout this essay. It occupies a specific position in a broader stack of physical denominators, and the correct denominator changes depending on what economic question is being asked:

Reading vendor numbers against this architecture. Vendor "per-rack" numbers refer to one NVL72 rack; "per-MW" numbers scale to 1000 kW / 120 kW per rack. GPU IT power (72 kW at 1 kW per GPU) is roughly 60% of the 120 kW rack; the other 40% is CPU + NVSwitch + memory + PDU losses. If a comparison mixes rack power and accelerator power without declaring which, its $/MW claim can be off by a factor of 1.5-2×.

So what. Any "content per MW" claim, including this essay's, is unusable in a comparative model unless it declares both the rack architecture and the MW definition it uses. Roughly half of the visible sell-side disagreement on AI-semi TAM resolves once both models are forced onto the same GB200 NVL72 / 120 kW / 8.33 racks / IT-MW basis. Underwriting discipline: reject any per-MW figure that omits its rack architecture and its MW definition; when you produce one, declare both. That reference-architecture filter kills more spurious analytical claims than any factual correction.

02Waterfall A. Compute silicon: ~$23M per MW

Compute accounts for roughly 67% of per-MW semiconductor content when all four waterfalls are counted, or ~92% when storage is excluded (the traditional AI-semi framing).

The B200 GPU is the anchor. At an approximate hyperscaler ASP of $35K per GPU (range $30-45K depending on volume and configuration), 600 GPUs per MW yields ~$21.0M in GPU spend alone. That ASP bundles the logic die, the HBM3e memory, and the CoWoS-L advanced packaging into one purchase price. The underlying production-cost stack, from Epoch AI's public teardown plus a residual for the balance of manufacturing lines that vendor filings do not itemise separately, reconciles as follows:

Sources: logic die + HBM + CoWoS lines from Epoch AI teardown; residual $1K covers substrate, package assembly, test, warranty reserve, and other manufacturing lines not itemised in the public teardown. The ~$28K is the gross-value spread between hyperscaler ASP and estimated production cost, not Nvidia accounting gross profit (see hero bullet 3).

The rest of the rack silicon adds another ~$2M per MW: Grace CPUs (36 per rack), NVSwitch die, ConnectX NICs, and the board-level VRM and POL silicon that regulates the compute die itself.

Vendor exposure. Five names capture most of the compute layer economics. Nvidia captures the GPU margin; TSMC captures the wafer and CoWoS margin; SK Hynix, Micron, Samsung capture the HBM margin. Hyperscaler custom silicon (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) shifts share off Nvidia but does not shrink the layer.

So what. The $23M/MW line is what Nvidia, TSMC, and the HBM triopoly are priced against; anyone underwriting these names without a specific view on where that line goes in 2027-2028 has an index bet, not a thesis. The two compressive variables to hold a view on: hyperscaler ASP negotiation outcomes on Blackwell/Rubin (a 20% ASP compression alone takes the layer from $23M to about $19.5M) and HBM3e supply-demand as Samsung + SK Hynix + Micron all ramp into 2027 (another 10-15% memory price compression takes it toward $19M). The bull case defends both variables; the bear case breaks either one. Read every quarterly hyperscaler capex disclosure and every HBM allocation update as a data point on one or the other.

02bThe denominator question, and the custom silicon path

The $23M-per-MW figure in the previous section prices at Nvidia hyperscaler ASP. Two reframes change what that number means.

Reframe one: silicon-vendor revenue vs Nvidia gross-value capture

Per Epoch AI's public teardown [P], a B200 costs approximately $6.75K to produce. The publicly itemised components sum to about $5.75K: $1.4K logic die + $3.25K HBM + $1.1K CoWoS. The remaining ~$1K covers substrate, package, test, warranty, and other manufacturing lines not separately itemised in the teardown. Across 600 GPUs per MW, 600 × $6.75K = $4.05M of estimated production cost is embedded in the accelerator stack, attributable primarily to TSMC (wafer + CoWoS), SK Hynix / Micron (HBM), and their OSATs (assembly / test / substrate) [D]. Note that BOM at estimated production cost measures a different quantity from realised supplier revenue: each supplier's actual revenue depends on their own gross margin over cost and on any allocation model between direct sales and packaged accelerator ASP. (If only the three publicly itemised components are counted, the number drops to 600 × $5.75K = ~$3.45M; the delta is the ~$1K/GPU other-mfg bucket noted above.) The remaining ~$17M per MW is the gross-value spread between hyperscaler ASP and estimated production cost. It is not Nvidia accounting gross profit or operating profit; the ASP-minus-BOM spread has to cover Nvidia gross margin plus board assembly, system-integration overhead, warranty reserves, R&D allocation, and other COGS lines before it reaches Nvidia's P&L. That ~$17M/MW spread is the specific dollar quantification of what every hyperscaler custom silicon programme is trying to internalise [I].

Reframe two: $/MW vs $/PFLOP

$/MW is a utility-bill number. It answers questions about facility electricity load, cooling design, and power-semiconductor content. It is the wrong number for comparing accelerator architectures that differ in compute-per-watt.

$/PFLOP is the compute-capacity number. Same silicon dollars, divided by delivered compute. Ranks vendors very differently:

The four active alternatives to Nvidia merchant GPU

Google TPU (Broadcom-designed, seven generations since 2014, current: Trillium v6e and Ironwood v7). Google captures the compute margin internally. Broadcom captures design fees and integration IP. Per Mizuho, Broadcom's Anthropic-related custom-silicon revenue reaches ~$21B in 2026 and roughly doubles to ~$42B in 2027 (Anthropic-specific; the Google TPU stream is positioned on top of this). On silicon-vendor cost basis, Google TPU delivers compute at approximately $1.75-4.0K per PFLOP, versus Nvidia's $18.5K per PFLOP hyperscaler ASP. Google internalises approximately $15-17M per MW that would otherwise flow to Nvidia.

AWS Trainium 2 (Marvell-designed). Project Rainier activated December 2025 with 500,000 Trainium 2 chips training Claude for Anthropic. Largest non-Nvidia cluster in production. Rental price $4.8/chip-hour vs Nvidia H100 $4-7/hr on-demand (2026). Amazon captures the compute margin internally; Marvell captures design fees.

AMD MI300X (merchant alternative). $15K purchase price with 192GB memory (2.4× H100's 80GB). Approximately 43% of Nvidia H100 price at same-generation performance for many workloads. On $/PFLOP basis: $11.5K vs Nvidia's $15.5K, roughly 40% cheaper per PFLOP. A merchant alternative that does not require hyperscaler-scale custom silicon investment.

Cerebras WSE-3 (wafer-scale, Cerebras-designed). Covered in dedicated detail in the next section because its economics require the $/PFLOP denominator to make sense.

The Broadcom shadow-Nvidia positioning

Broadcom guides to $56B AI semiconductor revenue in FY2026, with 10 GW of planned 2027 shipments and six confirmed XPU customers. By 2027, Counterpoint projects Broadcom captures approximately 60% of the custom AI ASIC market and Marvell approximately 25%. Broadcom is the specific vendor whose revenue grows as Nvidia's blended $/MW compresses. The two positions are inverse bets on the same variable: what percentage of AI compute is built on merchant Nvidia versus hyperscaler custom silicon over 2026-2028.

The custom-silicon capture bridge: what hyperscalers keep

A common misreading of the ~$17M-per-MW ASP-BOM spread treats it as free money a hyperscaler collects on switching to custom silicon. The reality differs. A functioning custom-silicon programme (Google TPU via Broadcom, AWS Trainium via Marvell/Annapurna, Microsoft Maia, Meta MTIA) redistributes the spread across four distinct cost lines before any residual reaches the hyperscaler P&L. The bridge below quantifies each deduction:

Two important consequences. First, custom silicon operates as a volume-scale programme. Treating it as a per-generation switching decision misses the NRE amortisation dynamics that decide whether the residual arrives at the hyperscaler's P&L. At single-GW fleet size, NRE alone consumes 3-5% of the spread and the whole bridge inverts. Hyperscalers only "win" versus Nvidia procurement past roughly 2-5 GW of cumulative custom silicon shipments, which is precisely why Google (14 years, seven TPU generations) captures more of the residual than Meta (first-generation MTIA v2 ramping). Second, Broadcom and Marvell are structural winners in the custom-silicon migration regardless of which hyperscaler wins the compute-market share war between them. Every custom silicon programme they design pays the ~$4.5M/MW design-service line. The custom-silicon migration thesis moves beyond primarily bearish Nvidia; it is primarily bullish AVGO + MRVL, with an ambiguous residual for the hyperscaler doing the internalising.

Sensitivity: custom silicon share swept 10% to 90%

The specific dollar impact depends on where custom silicon share lands. Sweeping the full plausible range; a single forecast would overstate the precision:

Today's baseline is approximately 15% custom silicon share (Google TPU deployments, AWS Trainium 2 Rainier cluster, Microsoft Maia early production, Meta MTIA v2 ramp). SemiAnalysis base case for 2028 assumes ~40%. Aggressive migration scenarios push toward 60-70% by 2030. Every quarterly hyperscaler custom silicon disclosure shifts the reader's placement on the sensitivity band.

Portfolio implication: Broadcom + Marvell are the leveraged play on rightward migration on the chart. Nvidia is the leveraged play on leftward stability. Neither position is symmetric: Nvidia loses $23M/MW × migration share, Broadcom + Marvell gain $5M/MW × migration share. The bear case for Nvidia centres on hyperscaler custom silicon migrating faster than consensus (not on AI slowing), and the compression is roughly 5:1 in favour of the incumbent shrinking (challenger growth stays smaller).

So what. The $23M-per-MW compute silicon line is Nvidia's ASP for hyperscalers who choose merchant GPU over custom, not a fixed industry fee. The alternative path exists and is actively expanding. Every quarterly disclosure of hyperscaler custom silicon build (Google TPU volumes, AWS Rainier scale-up, Microsoft Maia adoption, Meta MTIA v2 ramp) is a data point on how fast the merchant $23M-per-MW number compresses. Portfolio implication: Broadcom and Marvell are the leveraged play on the custom silicon migration; Nvidia is the leveraged play against it.

02cFalsification: does the waterfall survive architectural substitution?

An analytical framework is only as good as its behaviour under substitution. If the waterfall depends on Nvidia dominance, it collapses the moment merchant GPU share compresses. This section runs two formal substitution stress tests: wafer-scale silicon (Cerebras) and hyperscaler custom silicon (Google TPU, AWS Trainium). Both preserve the waterfall structure; only the vendor allocation and per-component quantities change. That is the important result.

Substitution A · Cerebras wafer-scale

Cerebras deserves its own subsection because the naive $/MW comparison is misleading in both directions. On the right precision basis, the picture is more nuanced than either Cerebras marketing or a superficial capex comparison suggests.

What Cerebras eliminates from the discrete-GPU stack

The Nvidia GB200 NVL72 rack (72 discrete GPU packages, 120 kW, $3.0M) holds hundreds of separate silicon components: 72 B200 dies in individual CoWoS-L packages, 576 HBM3e stacks, 18 NVSwitch die with NVLink SerDes, 36 Grace CPUs on 18 boards, 40+ ConnectX NICs, optical transceivers for external NVLink scale-out.

The Cerebras CS-3 (1 WSE-3 wafer, 23 kW, $3.0M) is a single monolithic wafer with 900,000 cores, 44GB of on-die SRAM, and on-wafer mesh interconnect at 21 PB/s aggregate bandwidth. External components: MemoryX (DRAM appliance for streaming model weights when they exceed 44GB) and SwarmX (fabric between wafers only). For working sets that fit in on-wafer SRAM, compute cycles avoid off-wafer memory traversal entirely; larger models still incur external-memory traversal, but at layer-streaming granularity; per-token traversal stays the alternative.

Two parity-compute cases: FP16 dense and FP16 sparse

Because Cerebras' architecture is optimised for sparsity, the comparison changes materially depending on whether the workload is dense or sparsity-friendly. Both are shown:

On FP16 dense, Cerebras requires 13 CS-3 systems to match a single GB200 NVL72 rack's throughput, consuming more silicon capex AND more electricity. Under the stated capex, power and utilisation assumptions, no commercially realistic electricity-price / deployment-life combination closes the dense-workload TCO gap through electricity savings alone. Cerebras loses on both denominators for dense workloads.

On FP16 sparse, Cerebras' architecture is more competitive. 2.6 CS-3 systems match the sparse throughput of one GB200 rack at $4.4M capex premium and ~81 kW power savings. The electricity-only breakeven equation below captures only the trade-off between Cerebras' higher upfront capex and its lower ongoing electricity draw. It excludes throughput-per-user premium, latency-priced revenue, utilisation differences, software-porting cost, staffing, maintenance, memory or storage differences, financing cost, and residual value. Real deployment decisions layer those on top.

At $80/MWh, the electricity-only breakeven takes ~86 years. At $300/MWh (premium market), still ~23 years. Even on Cerebras' architectural strength (sparse workloads), electricity savings alone do not justify the sparse-system capex premium in commercially realistic deployment horizons. If throughput-per-user premium, sovereign-compute pricing, or latency-priced inference revenue are added, the picture can flip; the base electricity math on its own does not close.

Where Cerebras' economics do work

The general-purpose TCO comparison does not favour Cerebras. Cerebras is built for specific workloads and deployment configurations where the framing changes:

1. Latency-critical single-user inference. Verified benchmark: Cerebras delivers 2,522 tokens/sec/user on Llama 4 Maverick vs Nvidia Blackwell's 1,038 tokens/sec/user (Artificial Analysis, May 2025). For interactive agent workflows, real-time developer tooling, or latency-priced inference products, the throughput-per-user premium can justify the silicon premium.
2. Power-constrained sites with sparse-friendly workloads. If site MW is capped by grid interconnection, and the workload can exploit sparsity, Cerebras delivers ~2× more sparse PFLOPS per MW than Nvidia (5,435 vs 2,700). The capex premium buys more compute per site MW budget. This works for sparse workloads only; on dense workloads, Nvidia delivers 2.5× more compute per MW.
3. Ultra-large model inference where the working set fits or streams cleanly. Cerebras' 44GB SRAM plus MemoryX for weight streaming can outperform HBM-tier fetch latency for specific inference patterns. Requires model architecture that maps well to the streaming pattern.
4. Sovereign compute deployments. India via G42 (8 exaflops planned), UAE via Core42, sovereign contracts prioritising non-Nvidia software stack. Strategic choice, not TCO-driven.

When Nvidia wins outright

1. Any dense-workload deployment. Training, dense inference, high-concurrency batch: Nvidia dominates on both capex and opex per PFLOP delivered.
2. Cheap-electricity sites. Cerebras' sparse-basis breakeven of L × P ~6,879 means at $80/MWh and 5-year life, Nvidia is ahead by roughly $4M per equivalent-sparse-compute unit over the deployment life.
3. Software ecosystem depth. CUDA, TensorRT, vLLM, existing pipelines. Migration cost is one-time but real.
4. Vendor scale and supply. Nvidia ships more B200s per quarter than Cerebras ships CS-3s in years. Supply reliability matters at hyperscale.

Substitution B · hyperscaler custom silicon

The second substitution: what happens to the waterfall if merchant GPU share compresses because Google TPU, AWS Trainium, Microsoft Maia, and Meta MTIA handle material share? Answer: the waterfall structure survives; only the vendor allocation shifts. Total semiconductor intensity per MW stays close to $34M (custom silicon needs the same HBM, storage, networking, and power infrastructure). What changes:

• Compute-waterfall dollars flow to Broadcom + Marvell (design fees) and TSMC + HBM triopoly (silicon-vendor share preserved) instead of to Nvidia. Nvidia's per-MW capture compresses as its market share falls (see sensitivity heat map in b).
• Storage, networking, and power waterfalls change negligibly. Custom silicon still needs SSDs, optics, switch ASICs, and power converters.
• HBM demand stays constant (custom accelerators use HBM3e too), so SK Hynix / Micron / Samsung revenue is largely indifferent to the merchant-vs-custom split.

Stress-test conclusion: the waterfall framework stays outside the Nvidia valuation model category. Total semiconductor intensity is preserved under both architectural substitutions tested here. What moves under substitution is the vendor allocation of waterfall dollars; the waterfall structure itself survives intact. That result validates the framework as a durable analytical unit; a point-in-time Nvidia-share forecast serves a different purpose.

So what. Cerebras is a specialist for sparse workloads at power-constrained or latency-critical deployments, not a general-purpose Nvidia alternative. The naive $/MW comparison hides that specialisation; correcting to FP16 dense vs sparse exposes it. For portfolio construction, Cerebras post-IPO belongs in a very different bucket than merchant GPU: it is a bet on sparse-friendly workloads dominating specific inference categories (agentic, low-latency); general AI compute displacement stays a different thesis. WSE-3 Turbo (250 PFLOPS sparse peak, announced 2026) doubles the sparse-basis throughput without changing the dense-basis story materially.

02dWaterfall D. Storage silicon: the workload-dependent waterfall, illustrative ~$9.0M per MW

The fourth semiconductor layer, usually excluded from the traditional compute/networking/power framing. Enterprise NVMe SSDs for training checkpoints, dataset caching, and inference-cache staging. Prices have risen approximately 320-450% since mid-2025 (industry aggregate) as hyperscaler orders outpace fab capacity.

Per current 30 TB enterprise TLC SSD pricing (approximately $22.6K per drive versus $3.5K in Q3 2025) [D], a representative provisioning of 20 TB per GPU across 600 GPUs per MW holds approximately $9.0M in NVMe silicon per MW. Global data centre SSD market: $50.2B (2025) rising to $62.0B (2026) [P].

The storage tiering behind the $9M number

The $9.0M storage figure covers more than one flash pool. Frontier AI training clusters run a two-tier storage architecture, and the two tiers have very different unit economics. Making the split explicit prevents the reader from thinking the number is arbitrary:

The Tier-0 line is why storage cannot be modelled as a single $/TB blended number. Local NVMe inside compute nodes prices at $1000-1400/TB for high-endurance mixed-use enterprise drives, roughly 2× the Tier-1 QLC blended average. The reader can rederive any $9M figure with different Tier-0/Tier-1 splits by substituting into the two lines above. Blended $/TB across both tiers ≈ $750, consistent with the earlier $9.0M figure. Alternative-decomposition sanity check: the same $9M can be reached under ~80 TB/GPU × 600 GPUs = 48 PB @ ~$187.50/TB blended, if the model uses lower-endurance QLC assumptions and heavier retention/caching. Both decompositions land at ~$9M/MW; the invariant is Storage TB per GPU × Blended $/TB × 600 = StI.

Storage provisioning sensitivity

Unlike GPU count, storage capacity per MW moves outside mechanical determination by rack power. Training workloads with frequent checkpointing need more storage; inference-heavy workloads need less. This makes the storage number the most assumption-heavy of the four waterfalls:

The base case number should be read as an illustrative provisioning point, not a firm per-MW physical constant like GPU count. This is the single largest source of range uncertainty in the total per-MW semiconductor figure.

Vendor exposure. Solidigm (SK Hynix subsidiary), Samsung, Kioxia, Micron, and Western Digital cover most enterprise NVMe supply. The four DRAM/NAND names in the compute layer (SK Hynix, Micron, Samsung, Kioxia) capture storage silicon revenue in parallel to their HBM revenue, but with very different unit economics: NAND is a commodity cyclical while HBM is a specialty allocated market.

So what. Storage silicon adds approximately 39% to the compute silicon layer per MW at the base case provisioning. Traditional AI semiconductor analysis excludes it, which understates per-MW content by ~26%. If SSD prices normalise as capacity ramps, this layer compresses faster than any other. If AI-cache demand outpaces fab expansion, it stays elevated. Watch quarterly NAND ASPs from Samsung, SK Hynix, and Micron for the leading indicator.

03Waterfall B. Networking silicon: ~$1.9M per MW (scale-out only)

Scale-up vs scale-out fabric: where each layer stays

Combined scale-up plus scale-out silicon per MW: ~$3.04M. Under the "networking-as-10-to-15%" convention (which counts scale-up), that ~$3.04M is ~8% of total semiconductor content, in line with prior-generation Hopper cluster references. Compute-share drops correspondingly.

Optical transceivers are the dominant line item within the scale-out fabric. At 3 pluggables per GPU (rack-to-spine plus scale-out, range 2-6 depending on topology and cluster size) and a blended ASP of $0.8K per module for 400G/800G optical, the transceiver spend for 600 GPUs sums to $1.44M per MW. Switch ASICs (Broadcom Tomahawk 5, Nvidia Spectrum-X, Nvidia Quantum InfiniBand) at $0.30M plus DPU and NIC silicon at $0.20M per MW bring the layer to $1.94M at typical port densities. Higher optics count (5-6 pluggables/GPU for 100K+ GPU pretraining clusters with 3-tier non-blocking fat-tree topology) pushes the scale-out line toward $3.20M per MW.

Vendor exposure. Split across two archetypes. Merchant switch silicon vendors Broadcom (Tomahawk, Jericho) and Marvell (Teralynx, Prestera) capture the ASIC layer. Optical component vendors Coherent, Lumentum, Ciena capture transceiver and laser silicon. Astera Labs and Credo capture the retimer and SmartNIC silicon that bridges the two.

Vendor transitions to watch. Copper-to-optical migration is the dominant technology question at the layer. Cluster sizes scaling from 8K to 100K+ GPUs roughly doubles active optical cable + pluggable content per GPU. EML and CW laser supply stay tight through the interim, which keeps pluggable transceiver ASPs firmer than a pure commodity market would suggest. Silicon photonics and co-packaged optics arrive over 2027-2029, not 2026.

So what. The networking layer forces two inverse underwriting bets on the same total dollar pool. Long the pluggable-optics ASP cycle through 2027-2028 (Coherent, Lumentum, Ciena on EML/CW laser tightness) or long silicon-photonics/CPO adoption from 2028 onward (Broadcom, Marvell capturing the next-generation transceiver socket). Pick one; you cannot own both at scale without doubling your exposure to a single cluster-networking dollar. A third asymmetric bet also hides here: any hyperscaler custom accelerator that internalises scale-up fabric inside the SKU (Nvidia NVSwitch already, AWS Trainium2 Neuron-Link next) shifts scale-up silicon revenue away from Broadcom/Marvell and into the accelerator basket. That is a Broadcom bear case rarely priced in consensus.

04Waterfall C. Power semiconductor: ~$300K per MW

The smallest of the layers in absolute dollars. The one that dominates trade coverage of the wide-bandgap sector. And the one that grows fastest in percentage terms as the 800V DC architecture transition adds SiC content at every stage from grid to processor.

The facility layer (medium-voltage grid interface, solid-state transformer if the site uses 800V DC, UPS power conversion) holds approximately $50K of SiC device content per MW. The rack DC-DC layer (800V→48V bus conversion) adds $80K of mixed SiC and GaN content. The board VRM layer (48V→12V) adds $70K, primarily GaN. The point-of-load layer (12V→processor VCORE) adds $100K of silicon and GaN content in aggregate. Total per MW: approximately $300K across the $180-$570K range.

The onsemi anchor. Onsemi disclosed on its Q1 2026 earnings call that its own power semiconductor content per next-generation 1 MW AI rack has doubled from approximately $50K prior generation to $100K next-generation. That is one vendor across a portion of the stages. Grossed up for the 5-6 major power semiconductor vendors that supply the full stack, the industry total is approximately $300K per MW today, on track to $750K by the Rubin generation.

Vendor exposure. Infineon and STMicroelectronics: broad-line IDMs across SiC and Si. Wolfspeed: SiC substrate + device stack. onsemi: SiC + GaN combined with automotive scale. Navitas Semi, EPC, Innoscience: pure-play GaN. Power Integrations: system-integration with GaN roadmap extending to 1700V. See the wide-bandgap stack essay for the vendor-level breakdown of SiC vs GaN market share.

So what. The 800V DC transition thesis is falsifiable on quarterly cadence. Three leading indicators move first: onsemi's per-MW content disclosure (already doubled Q1 2026 versus prior generation), Infineon's SiC data-centre revenue line, and Wolfspeed's design-in wins on the 2027-generation rack. If per-MW power semi content walks from $300K to $750K by Rubin, that is a 2.5× multiplier concentrated in seven public names, enough to reprice the entire wide-bandgap complex. If the transition slips another two years, the same names de-rate against consensus. This layer is small in absolute dollars but large in variance, and the variance moves on disclosures that publish quarterly.

05Composition, sensitivity, and the constraint ladder

Composing the layers together gives the total silicon spend per MW. The split is more extreme than sector-level analyst frames typically suggest, because storage is usually excluded from "AI silicon" but represents roughly a quarter of per-MW silicon content once you include it.

The AI MW BOM: reference case, September 2026

Citeable single-page reference for a Blackwell-generation 1 MW IT load. Every downstream calculation in this essay derives from this table.

Reference: Blackwell-generation GB200 NVL72 platform, hyperscaler-configured pricing, September 2026. Numbers pull from the modular Python generator; every value is reproducible. Range across the sensitivity matrix below: ~$26M to ~$49M per MW.

Sensitivity matrix: semiconductor intensity across plausible architectures

Two dimensions dominate the range: GPU ASP (a market variable) and storage provisioning (an architectural choice). Cells show total semiconductor intensity ($/MW) at each combination. The reference case is the $35K × 20 TB centre cell.

Formula: 600 × GPU ASP + 600 × storage TB × $0.75K/TB + $4.24M (rack silicon + networking + power semi, held constant). Semiconductor intensity spans $26.7M – $49.2M per MW across this 3 × 3. Reference case ($35K × 20 TB) = $34.24M represents the mid-range point of that band; read it as a reference case; a universal constant would overstate the generality.

Content elasticity: which variable moves semiconductor intensity

Ranking the six most-consequential drivers:

So what. GPU ASP is by far the highest-elasticity variable (10% ASP move = 6.1% intensity move). Storage volumes and NAND ASP are joint second at ~2.6%. Everything else is <2%. The practical implication for forecasters: the $34M number moves primarily on Nvidia ASP negotiations and hyperscaler storage provisioning choices; optical mix, networking silicon, and power semiconductor content contribute rounding noise at the MW-total level. This is orthogonal to vendor impact: a small elasticity at the aggregate level can still translate into large equity moves for a small-market-cap specialist vendor.

An interesting side-observation. Most AI-semiconductor frameworks exclude storage, which produces the more familiar compute / networking / power split of approximately 92 / 6 / 1. Once storage is included on the same denominator, the picture reranks to 67 / 26 / 6 / 1. Storage silicon is the second-largest per-MW semiconductor line at roughly 26% of total content, driven by the 5.4× SSD price rise since mid-2025 and by checkpoint frequency, retention policy, dataset caching, and model scale on the demand side.

So what. The ratio of compute silicon spend to power silicon spend per MW (77×) is the most useful mental anchor for reading AI-infrastructure equity coverage. When a report says "AI-driven semiconductor content is growing 30% per year," check which layer is being counted. Compute-layer 30% growth is ~$7M per MW of incremental spend. Storage-layer 30% growth is ~$2.7M. Power-layer 30% growth is ~$90K. Same percentage, radically different dollar impact and radically different vendor sets.

The basket-denominator table

Each vendor basket has its own natural economic denominator. Reading equity research becomes much cleaner once these are separated:

The constraint ladder: seven binding constraints, seven correct denominators

The single most portable idea in this essay stays here. The correct economic denominator changes depending on which resource is scarce. This is the deeper reason $/MW alone cannot answer every AI-infrastructure question. The waterfall answers the $/MW view; the ladder below converts that answer into whichever denominator matches the reader's own bottleneck:

Three canonical denominators, three canonical readers

Compressed further: three denominators do most of the analytical work in AI-infrastructure valuation. Each answers a different question, each identifies a different winner, and each has its own institutional constituency. Reading equity coverage becomes cleaner once these three are separated:

Reranking rule: the top performer under one denominator shifts under the others. Nvidia dominates $/MW because dense packaging plus bundled ASP concentrates silicon value per rack. Google TPU dominates $/PFLOP because vertical integration eliminates the merchant margin the second table in b quantifies. Cerebras and Groq dominate $/token/sec on latency-priced workloads because SRAM-bandwidth architectures bypass the HBM fetch penalty that limits token generation on discrete-GPU stacks. Portfolio construction under a single denominator is a well-defined mistake.

Every AI-infrastructure investment thesis implicitly bets on one of these being the binding constraint. The essay's core waterfall answers the question that assumes $/MW is the frame. The constraint ladder above allows readers to translate that answer into the right economic denominator for whatever bottleneck they see coming next.

06Trajectory: Hopper → Blackwell → Rubin

Content per MW moves with each generation. Each Nvidia generation increases GPU count per rack, HBM capacity per GPU, and (from Rubin onward) drives the 800V DC transition into the rest of the stack.

Two comparable views across three generations. CORE (ex-storage) is the traditional AI-semi frame: compute + networking + power semiconductor only, comparable across generations before storage provisioning became a first-class per-MW line. FULL (inc-storage) adds the fourth waterfall at each generation's storage provisioning and NAND pricing:

• Hopper 2023 (H100 / H200): CORE ~$15.2M/MW, FULL ~$18.6M/MW. Rack power ~40 kW air-cooled or early liquid-cooled. Compute $14M, storage ~$3.5M (at pre-2025 NAND prices), networking $1.0M, power $150K.
• Blackwell 2025 (B200 / GB200): CORE ~$25.24M/MW, FULL ~$34.24M/MW, which is the reference case for the whole essay. Rack power 120 kW liquid-cooled. Compute $23M, storage $9.0M (post-2025 NAND spike), networking $1.94M, power $300K.
• Rubin 2027 MODEL (illustrative): CORE ~$43.8M/MW, FULL ~$58.8M/MW at midpoint. Rack power ~250 kW liquid-cooled with 800V DC bus. Compute $40M ± 20%, storage $15M, networking $3.0M, power $750K. All 2027 numbers depend on GPU generation ASP holding, HBM3e allocation, CoWoS-L capacity, and whether NAND prices soften as fab capacity ramps.

The macro conclusion. The AI buildout adds silicon intensity per MW, with MW growth as a secondary vector. Each successive MW is becoming more silicon-intensive under both views. CORE: Hopper to Blackwell +67%, Blackwell to Rubin (modelled) +73%, Hopper to Rubin ~2.9×. FULL: Hopper to Blackwell +84%, Blackwell to Rubin +72%, Hopper to Rubin ~3.1×. AI power demand is the top-line story; per-MW semiconductor content escalation is the compounding one. The storage waterfall is what pushes FULL above CORE by roughly $9M today and rises further as workload complexity increases.

Growth is uneven across the four waterfalls. Compute silicon roughly triples Hopper to Rubin. Networking silicon triples. Power silicon roughly quintuples from $150K to $750K per MW, driven almost entirely by 800V DC adoption pulling SiC content into facility and rack layers that had no SiC at 48V. Power silicon grows fastest in percentage terms while staying the smallest in absolute terms.

So what. Per-MW content compounding is what protects the AI-semi complex against MW-buildout slowdown. Even under a scenario where installed AI MW growth halves versus current consensus, the ~3× per-MW content escalation from Hopper to Rubin sustains revenue growth for accelerator, HBM, and power-semi vendors. The bear case for AI semis works through single-vendor per-MW share compression (Nvidia losing ASP to custom ASIC migration faster than the aggregate escalates); aggregate MW-buildout deceleration matters less than the vendor-mix shift. Underwriters need a view on both variables, MW build rate AND per-MW content growth by layer, before extrapolating any single-vendor forecast forward.

07Vendor exposure map by basket

Same MW of AI installed base drives revenue across all six investment baskets, at very different scales and with very different vendor concentrations. The four-waterfalls-to-six-baskets mapping reflects that within the compute waterfall alone there are three distinct vendor archetypes (merchant GPU, custom silicon design, memory + packaging) that trade differently.

Basket 1: Merchant GPU accelerator. Extremely concentrated. Nvidia captures the majority of the $21M-per-MW GPU line at hyperscaler ASP; AMD MI300X provides a merchant alternative at roughly half the $/PFLOP.

Basket 2: Custom silicon design. Broadcom (Google TPU, OpenAI custom, plus four other XPU customers) and Marvell (AWS Trainium, Microsoft Maia) capture the design fee + IP royalty from every custom accelerator shipped. Broadcom guides to $56B AI silicon revenue in FY2026 and 10 GW of planned 2027 shipments. Shadow-Nvidia positioning: revenue grows as Nvidia's blended $/MW compresses.

Basket 3: Memory + advanced packaging. TSMC (CoWoS-L near-monopoly), SK Hynix (HBM3e leader), Micron and Samsung (HBM3e ramp). These are the silicon-vendor cost basis inside the $23M compute line: what gets paid to fabs and memory makers regardless of whether the GPU brand is Nvidia, AMD, or a hyperscaler custom part.

Basket 4: Storage NAND / SSD. Solidigm (SK Hynix subsidiary), Samsung, Kioxia, Micron, Western Digital. Roughly $9M per MW at the base provisioning case, $4.5-$18M range. NAND is a commodity cyclical; the AI-driven price spike since mid-2025 may or may not persist as fab capacity ramps.

Basket 5: Networking silicon. Two sub-groups. Merchant switch silicon consolidated at Broadcom and Marvell. Optical component silicon at Coherent, Lumentum, and specialty players. Retimer and SmartNIC silicon at Astera Labs and Credo. All grow with installed cluster count; silicon photonics adoption timing determines which specific vendors capture the next-generation transceiver market.

Basket 6: Power semiconductor. Seven public names cover most of the $300K-per-MW line: Infineon, STMicroelectronics, onsemi, Wolfspeed, Navitas, Innoscience (Hong Kong-listed), Power Integrations. Rohm and EPC (private) round out the vendor list. Multiples price growth optionality against a small absolute revenue number.

From equipment ASP to supplier revenue: the capture chain

Every dollar in the waterfall table represents equipment ASP. That dollar flows down through several transitions before reaching semiconductor-supplier revenue: equipment ASP → component-supplier revenue → semiconductor-supplier revenue → semiconductor-supplier gross profit. Each transition compresses the number, often by 30-50%. Worked example on storage: a $9M waterfall converts to roughly $5-6M of NAND-supplier revenue and $2-3M of NAND-supplier gross profit; the balance rides controller silicon, DRAM cache, PCB, form-factor assembly, firmware, and channel margin. On networking: the $1.94M waterfall converts to roughly $1.0-1.3M of optical-component + switch-ASIC supplier revenue, with the balance in transceiver housing, connectors, optical fibre, and system integration.

Define vendor value capture as supplier-attributable revenue divided by waterfall value. Ratios vary materially across baskets:

• Compute waterfall: Nvidia + TSMC + HBM triopoly capture ~$18-20M of the $23M waterfall in supplier revenue (~80-87% capture); Nvidia alone claims ~$21M of the equipment ASP as its own line. High capture ratio because compute equipment IS silicon.
• Storage waterfall: NAND suppliers capture ~$5-6M of the $9M waterfall in supplier revenue (~55-65% capture); the balance is controller silicon, DRAM cache, PCB, form-factor assembly, firmware, and channel margin.
• Networking waterfall: Optical component + switch ASIC suppliers capture ~$1.0-1.3M of the $1.94M waterfall (~55-70% capture); balance is transceiver housing, connectors, optical fibre, and system integration.
• Power semiconductor waterfall: SiC + GaN device suppliers capture ~$150-200K of the $300K waterfall (~50-65% capture); balance is passives, copper, iron, enclosure, thermal management, and system integration in the SST / UPS / DC-DC modules.

The compute-basket capture ratio is why NVDA, TSM, and SK Hynix trade on multiples that reflect near-full pricing power over the $23M waterfall. The power-basket capture ratio is why Infineon / STMicro / onsemi trade on multiples that reflect ~50-65% of the $300K figure. Cross-basket comparisons of "AI semiconductor exposure" that ignore value-capture ratios systematically over-attribute revenue to the smaller baskets.

So what. Portfolio construction across the baskets requires accepting genuinely different risk profiles at basket level, not a single sector-level view. Merchant GPU holds ASP compression risk from custom-silicon migration. Custom silicon design depends on hyperscaler in-sourcing pace. Memory + packaging faces HBM oversupply after 2027. Storage rides the NAND cycle. Networking turns on copper-vs-optical transition timing. Power semi depends on 800V DC adoption pace and EV-demand pull on SiC capacity. Installed AI MW is the shared demand driver; the vendor-specific risk factors are distinct enough that a sector-level bear or bull case averages them into noise.

08What could break each waterfall

Every $/MW number above depends on structural assumptions. The specific failure modes for each waterfall:

Compute waterfall risk factors

• Hyperscaler custom ASIC (TPU, Trainium, MTIA) shifts share off Nvidia (same silicon spend, different vendor line)
• HBM oversupply after 2027 as Samsung + SK Hynix + Micron all ramp, which could compress $/GB by 20-30%
• Advanced packaging (CoWoS-L) capacity outpaces demand (unlikely near-term but worth watching TSMC quarterly disclosures)

Networking waterfall risk factors

• Copper stays dominant longer than expected (200G/400G on copper for shorter reach)
• Optical adoption slower if 800G/1.6T scaling delayed
• In-house switch silicon at hyperscalers reduces merchant ASIC share

Power waterfall risk factors

• 800V DC adoption delayed beyond 2028, which keeps 48V DC content per MW compressed
• EV demand comes back stronger than forecast, pulling SiC capacity to automotive and leaving DC-power vendors under-supplied
• Chinese GaN and SiC price war extends further into Western hyperscaler qualification pipelines

So what. Each waterfall holds different risk factors capable of compressing the $/MW number by 20-40%. Nvidia ASP compression and HBM oversupply are the compute-basket risks, tracked through hyperscaler quarterly capex commentary and HBM supplier allocation guidance. Networking bears the copper-persistence and hyperscaler-insourcing risks; both print in pluggable transceiver ASPs and merchant switch-ASIC share. Power depends on 800V DC deployment holding its 2027-2028 schedule at facility and rack level; a two-year slip re-rates the whole wide-bandgap complex. Track on quarterly cadence (sector-level treatment stays coarser).

09Actionable close and what comes next

The four-waterfall framework produces four specific portfolio-construction takeaways:

1. Semiconductor intensity ($/MW) is the durable unit of account. A 1 MW Blackwell-generation reference configuration holds approximately $34M of semiconductor-bearing equipment value across four waterfalls: $23M compute, $9M storage, $1.9M networking, $300K power. Full-stack split is 67/26/6/1. The ex-storage traditional split is 92/6/1. Reference case sensitivity across GPU ASP × storage provisioning spans ~$26M-$49M/MW. The number is architecture-dependent; the denominator stays stable.
2. Rubin-generation inflection compounds unevenly across the four waterfalls. Content per MW roughly doubles by 2027 (~$59M). Power silicon grows fastest in percentage terms because the 800V DC transition adds SiC across cascade stages. Compute and networking grow steadily. Storage compression or persistence is the swing variable.
3. Vendors by basket (details):
   • Merchant GPU: NVDA, AMD
   • Custom silicon design: AVGO, MRVL
   • Memory + advanced packaging: TSM, SK Hynix, Micron, Samsung
   • Storage NAND: Solidigm, Samsung, Kioxia, Micron, WDC
   • Networking silicon: AVGO, MRVL, COHR, LITE, ALAB, CRDO
   • Power semiconductor: IFX, STM, ON, WOLF, NVTS, EPC, Innoscience, POWI
4. Falsifier structure works at basket level. Compute-waterfall risk is Nvidia ASP compression on Blackwell/Rubin; a 20% ASP move plus 15% HBM softening walks the compute layer from $23M/MW to $19M. On networking, the question is copper-vs-optical timing. If 400G/800G copper persists past 2027-2029, pluggable transceiver ASPs compress faster than consensus. Power semi rides the 800V DC schedule at facility and rack level; onsemi's next per-MW disclosure prints the leading indicator. Each of these operates on a different cadence and touches a different vendor set; a sector-level bear case averages them into noise.