Physical infrastructure · power sidecar

The 800V DC Power Sidecar: Anatomy, Conversion Boundary, and Where the Value Moves

The power sidecar is a rack-adjacent power-conversion object that moves some or all of the AC/DC and ride-through function out of the compute rack. In the 800V-class architectures examined here, it can hand an 800V DC bus directly to the compute rack or perform an additional DC/DC conversion before distribution. OCP Diablo 400 establishes a ±400V bipolar reference architecture, alongside other 350/700V and unipolar configurations in the broader LVDC work, on a rolling path toward native 800V distribution at the facility. The sidecar exists because compute density has moved past what a compute-plus-power-plus-thermal rack can handle. What follows: the 10-layer BOM, the conversion boundary that decides where the value gets captured, and what changes when 800V goes native.

Reader takeaways
What it is
Rack-adjacent object that converts an existing 480 VAC-class feed to ~800V DC (bipolar or unipolar) and hands it to the compute rack via a busbar drop.
Anchor reference
Delta 660 kW in-row: six 110 kW shelves, each with 80 kW BBU, powered by 18.5 kW AC/DC PSUs. Delta separately ships a 1RU 90 kW 800V→50V DC/DC shelf and 1 MW-class in-row systems.
The conversion boundary
Whether the sidecar hands ~800V DC directly to the rack (Option A, high-voltage direct) or steps down to 48V inside the sidecar (Option B) is the strategic architectural fork. At 1 MW, Option B implies ~20.8 kA between sidecar and rack.
Native 800V spans several topologies
OCP LVDC covers 350/700V bipolar TN-S with distributed midpoint, without distributed midpoint, IT variants, and 700V unipolar TN-S / IT. Grounding, protection, connector requal and SiC device class differ across each.
Value migration
Every conversion arrow that disappears from the stack destroys a conversion market. Every arrow that remains concentrates value into the vendor that owns it. So the question is which vendor owns the surviving stages.

01What a sidecar is, and why now

As an illustrative density progression, this analysis uses ~8-15 kW/rack for pre-AI systems, ~30-60 kW/rack for H100-class dense racks, and 100+ kW rack-scale (GB200/GB300 NVL72 at ~120-140 kW per NVIDIA reference architecture) for the frontier (author's synthesis of published vendor and OCP platform specifications, not an industry census). The rack that used to accommodate compute plus power plus thermal cannot host all three at this density. Something has to move out. The sidecar is the physical answer: pull AC-DC conversion and battery ride-through into a rack-adjacent object so the compute rack is free for silicon.

Figure 1
The power sidecar. Facility AC to DC bus to compute rack
FACILITY LV Switchboard 380-480 VAC 3-phase from grey-space plant Existing infrastructure AC IN POWER SIDECAR The rack-adjacent object Layers 01-10 (see Figure 3) AC input + protection AC-DC conversion (highest-value slot) Energy storage + ride-through DC bus + protection Controls + comms Busbar drop Six functional families, ten layers ~800V DC OUT Bipolar ±400V today, Diablo 400 v0.5.2 COMPUTE RACK GPU / accelerator rack 100+ kW/rack GPU tray GPU tray Rack DC-DC (~800V → 50V) Vicor / MPS / Navitas / EPC on tray or backplane FUTURE STATE Native 800V facility MV AC to ~800V DC via facility-level SST Sidecar bypassed at 800V-native sites AC path (facility) DC path (sidecar) The sidecar is the transitional architecture that allows 800V rack power to arrive before the facility itself becomes native 800V.
The sidecar is the AC/DC boundary object. AC in from existing switchgear on the left, ~800V DC to the compute rack on the right. Rack DC/DC (Vicor / MPS / Navitas / EPC) does the final drop to GPU rails inside the compute chassis. The dashed panel on the right is the future-state facility architecture that removes the sidecar entirely.

02The concrete anchor. Delta 660 kW

The Delta 660 kW in-row is the useful publicly disclosed commercial reference point in this analysis. It grounds the architecture in an announced product; specification-abstraction framing stays weaker.

Figure 2
Delta 660 kW anatomy. Six 110 kW shelves, 80 kW BBU per shelf, 18.5 kW PSUs. 90 kW DC/DC is a separate Delta product; it does not sit inside the 660 kW sidecar.
660 kW SIDECAR RACK · SIDE VIEW Six 110 kW shelves stacked vertically Shelf 6 · 110 kW 80 kW BBU Shelf 5 · 110 kW 80 kW BBU Shelf 4 · 110 kW 80 kW BBU Shelf 3 · 110 kW 80 kW BBU Shelf 2 · 110 kW 80 kW BBU Shelf 1 · 110 kW 80 kW BBU SHELF DETAIL (110 kW) Per-shelf composition 18.5kW 18.5kW 18.5kW 18.5kW 18.5kW 18.5kW Six 18.5 kW AC/DC PSUs = ~111 kW shelf output 80 kW BBU integrated per shelf 6 shelves × 80 kW BBU = 480 kW total BBU across the rack SEPARATE PRODUCT · 1RU 90 kW DC/DC 1RU 90 kW 800V → 50V DC/DC Layer 05 (compute-chassis resident under HV-direct topologies). Delta ships this shelf separately from the 660 kW rack. Not part of the 660 kW BOM allocation shown in Figure 4. TOTALS · 660 kW SIDECAR Delta 660 kW in-row totals Total continuous output 660 kW 6 shelves × 110 kW Total BBU capacity 480 kW 6 shelves × 80 kW BBU each AC/DC PSU count 36 x 18.5 kW 6 PSUs per shelf Sidecar category range Hundreds of kW → 1 MW+ Delta also ships 1 MW-class in-row systems in this category Useful current commercial reference, not the market-defined standard.
Delta 660 kW in-row: six 110 kW shelves stacked, each with six 18.5 kW AC/DC PSUs delivering ~111 kW and integrated 80 kW BBU. Total 480 kW BBU across the rack. The 1RU 90 kW 800V-to-50V DC/DC shelf is a separate product and typically belongs to the compute chassis under HV-direct topologies.

03The 10-layer BOM

Ten functional layers grouped into six functional families. Layer 05 is conditional. Under HV-direct topologies it belongs to the compute chassis; sidecar placement sits elsewhere.

Figure 3
Sidecar BOM (SIDECAR ONLY). Ten layers grouped into six functional families
A. AC INPUT 01 Input + protection 380-480 VAC 3-ph MCCB, EMI/EMC filter, SPD, phase monitoring B. AC-DC CONVERSION 02 AC-DC conversion AC to ~800V DC via modular high-frequency AC/DC power stages Delta ref: 18.5 kW PSUs supporting 110 kW shelves Predominantly SiC Highest single BOM slot C. ENERGY STORAGE 04 Storage + ride-through Three time horizons: • Capacitor: ms-s   (GPU transient smoothing) • Battery: ~60-90 s   (shelf ride-through, Al-cap) • Facility BESS: min-hr   (outside sidecar) D. DC BUS + PROTECTION 03 DC bus structure Bipolar +400/mid/-400V (Diablo 400 v0.5.2) or 700V unipolar per topology 06 Protection + monitoring Requirements depend on grounding topology. Diablo: GFD + midpoint; IT variants use IMD. E. CONTROLS + INTEGRATION 07 Controls + comms PLC, EPMS/BMS handoff, redundancy manager, cyber 09 Thermal Diablo 400: air-cooled Future/high-density: liquid possible 10 Cabinet + physical OCP 21" or hyperscaler custom. EMC shielding, seismic bracing, fire-suppression compatibility. F. RACK HANDOFF 08 Busbar drop to compute rack Blind-mate DC busbar connector. Continuous current + voltage rating is topology-dependent (see §08). Vendors: Amphenol · Anderson Power · Molex TE Connectivity · Harting Rack integrator: Rittal, Delta CONDITIONAL · COMPUTE-CHASSIS RESIDENT 05 DC-DC intermediate Sidecar hands ~800V DC to the rack. Intermediate step-down (to ~48V) belongs to the compute tray under HV-direct topologies. See §08 conversion boundary. Vicor, MPS, Navitas, EPC territory READING GUIDE Ten layers. Six functional families. Vermillion-filled layers are highest-BOM-value slots. Dashed-border Layer 05 is conditional: whether it belongs to the sidecar or the compute tray depends on the architectural fork covered in §08. Layer 04 storage decomposition: Capacitor (Delta EVA-style), battery (Delta 660 kW: 6 × 80 kW), and facility BESS. Only the first two are physically inside the sidecar. Delta 660 kW: 6 × 110 kW shelves · 480 kW total BBU 36 × 18.5 kW AC/DC PSUs
The 10-layer BOM organised into six functional families. Layer 02 (AC-DC conversion) is the highest-BOM-value slot; Layer 04 (energy storage) is analysed across three time horizons but the sidecar contains only the first two (capacitor and battery); the third (facility BESS) is upstream at facility level. Layer 05 is conditional and typically belongs to the compute chassis; sidecar placement sits elsewhere.

Per-layer semiconductor detail and vendor field:

#LayerSemiconductor contentVendor examples
01Input + protectionSPD: MOV / TVS / GDT depending on protection architecture; passive elements. TVS or semiconductor protection devices where used.ABB, Eaton, Schneider, Littelfuse
02AC-DC conversionSiC MOSFETs + Schottky (primary path); Si IGBTs on cost-sensitive stagesIntegrators: Delta, LITEON, Chicony, Flex, Bel Power, Advanced Energy · SiC: Wolfspeed, onsemi, STMicro, Infineon
03DC bus structureSemiconductor contactor drivers (Si); passiveMersen, Eaton, ABB, Amphenol, Rittal
04Storage + ride-throughBattery MOSFETs (Si LV), BMS ASIC (Si)Cells: CATL, EVE, BYD, LG · BMS: ADI, TI, Renesas, NXP · Capacitors: KEMET, Murata, TDK
05DC-DC intermediate (compute-chassis conditional)SiC (medium-ratio stage); GaN (high-frequency post-reg)Vicor, MPS, Navitas, Ferric, EPC, Advanced Energy
06Protection + monitoringHall-effect sensors, IMD/GFD ICs, AFDD MCUBender, Littelfuse, Eaton, Siemens, Schneider, LEM, Allegro
07Controls + commsMCU, FPGA, secure elementDelta (in-house), Beckhoff, ABB, Emerson, Siemens
08Busbar dropMechanical + insulator; no active semiconductorAmphenol, Anderson Power, Molex, TE Connectivity, Harting · Rack: Rittal, Delta
09Thermal managementFan drivers (Si); no primary semiconductor contentDelta (integrated), Sanyo Denki (fans), CoolIT/Ecolab (liquid), Boyd
10Cabinet + physicalNoneRittal, Delta, Legrand, nVent, Chatsworth

04Where the dollars sit

Illustrative BOM allocation ex-Layer-05. AUTHOR SCENARIO with declared baseline. Sensitivity to BBU duration in Figure 5.

Figure 4
BOM allocation (SIDECAR ONLY, ex-Layer-05). Layer share of estimated equipment-level hardware value at ~660 kW reference. AUTHOR SCENARIO, not disclosed supplier BOM.
AUTHOR SCENARIO · NOT A DISCLOSED SUPPLIER BOM 0% 10% 20% 30% 40% 50% Layer 02 · AC-DC conversion 35-45% Layer 04 · Energy storage 20-30% Layers 03 + 06 · DC bus + protection 8-12% Layer 09 · Thermal management 4-8% Layers 01 + 10 · AC input + cabinet 5-8% Layer 07 · Controls + comms 4-6% Layer 08 · Busbar drop + connectors 3-5% Layer 05 · excluded (compute-chassis resident) Not counted — see §08 DECLARED BASELINE Topology: 480 VAC → ±400 VDC active PFC; N+1 redundancy on rectification. Reference size: ~660 kW sidecar (Delta 660 kW is a useful current commercial reference). BBU sizing: ~60-90 sec aluminum-capacitor ride-through baseline; verify against product-specific spec. Stretching to 3-5 min distorts Layer 04 past ~35% of the allocation (see Figure 5). Layer 05 treatment: excluded from the ex-Layer-05 100% total to prevent double-counting with compute-tray DC/DC. Author estimates only; supplier quotations and disclosed product BOMs are outside the source set.
Layer 02 (AC-DC) is the single largest BOM slot at 35-45%. Layer 04 (energy storage) is the second-largest at 20-30% under a 60-90 second BBU baseline. Baseline strip below the chart declares the topology, BBU sizing and Layer 05 treatment that anchor the scenario.

05How sensitive is that to BBU duration

At fixed power and chemistry, required stored energy scales approximately with ride-through duration. The resulting Layer 04 BOM share is therefore directionally sensitive to duration, though not necessarily linear in a real implementation.

Figure 5
BBU sensitivity (SIDECAR ONLY). Layer 04 share of estimated hardware value as ride-through duration extends
AUTHOR SCENARIO · SENSITIVITY ILLUSTRATION 50% 40% 30% 20% 10% 0% 0 60s 90s 180s (3 min) 300s (5 min) 600s (10 min) AUTHOR SCENARIO 60-90 SEC BASELINE (not an OCP spec) Layer 04 > 35%: other slots start to compress ~22% ~28% ~35% ~45% ~55% Layer 04 · % of BOM value Reading the sensitivity. At the 60-90 sec baseline, Layer 04 accounts for 22-28% of BOM value. Extending to 3 min (~35%) is the point at which other slots start to compress. Beyond 5 minutes, Layer 04 dominates the allocation and the structure of the pie changes materially.
Required stored energy scales approximately with ride-through duration at fixed power. The resulting Layer 04 BOM share is scenario-dependent and becomes increasingly non-linear as storage dominates the architecture. Fixed components (power electronics, enclosure, thermal design, redundancy, integrator margin) do not scale linearly. Baseline used here is ~60-90 seconds; beyond ~3 minutes, storage hardware starts to squeeze Layer 02 and the other slots.

06The semiconductor map

Layer-by-layer semiconductor content in the sidecar, mapped by device family.

Figure 6
Semiconductor content by layer (SIDECAR ONLY). Where Si, SiC, GaN, sensors and MCUs sit
SiC MOSFET SiC Schottky GaN HEMT Si (LV MOS, IGBT) Sensors + Hall MCU / FPGA 01. Input + protection SPD (MOV/TVS/GDT) phase monitor 02. AC-DC conversion PRIMARY PRIMARY cost-sensitive stages current, temp shelf controller 03. DC bus structure DC contactor drivers 04. Storage + ride-through battery MOSFETs cell V/T sense BMS ASIC 05. DC-DC (compute chassis) medium-ratio high-freq post-reg LV MOS current sense rail controller 06. Protection + monitoring Hall, IMD, GFD AFDD MCU 07. Controls + comms PRIMARY 08. Busbar drop 09. Thermal management fan drivers temp sense 10. Cabinet + physical Primary content Secondary content Absent at this layer VENDOR EXAMPLES SiC: Wolfspeed, onsemi, STMicro, Infineon  ·  GaN: Navitas, EPC, Infineon  ·  Sensors: LEM, Allegro, Bender (GFD/IMD)  ·  MCU/FPGA: TI, ADI, Renesas, ST, NXP
SiC concentrates in Layer 02 (AC-DC) and Layer 05 (compute-chassis DC-DC). GaN is most relevant to Layer 05 post-regulation in architectures that use a high-frequency GaN stage. Si low-voltage MOSFETs and IGBTs populate cost-sensitive stages, battery switching and DC contactor drivers. Sensors and MCUs recur across protection and control layers. Layers 08 and 10 include no material semiconductor content.

07Semiconductor value by device family

Figure 6 maps presence. Figure 7 maps economic weight. Where the semiconductor dollars concentrate across the sidecar plus the compute-chassis DC/DC that hosts Layer 05.

Figure 7
Semiconductor value per MW by device family (SIDECAR + COMPUTE DC/DC combined). AUTHOR SCENARIO on component economics, not supplier revenue.
AUTHOR SCENARIO · COMPONENT ECONOMICS, NOT SUPPLIER REVENUE $0 $2k $4k $6k $8k $10k+ Illustrative $/MW at sidecar + compute-chassis DC/DC combined SiC MOSFET Layer 02 primary + Layer 05 $5-10k/MW SiC Schottky Layer 02 primary $1.5-3k/MW Si LV MOSFET + IGBT Cost-sensitive stages, battery, contactors $1-2k/MW GaN HEMT Layer 05 post-regulation (compute chassis) $0.5-1.5k/MW Sensors + Hall + IMD/GFD Layer 06 primary, ubiquitous elsewhere $0.3-0.7k/MW MCU / FPGA / BMS ASIC Every controls layer $0.2-0.5k/MW Author estimates only. Supplier quotations are outside the source set. Ranges compound the sidecar and compute-chassis DC/DC contributions; splitting them across the Layer 05 conditional boundary (§08) redistributes the SiC and GaN totals materially.
SiC MOSFETs capture the largest semiconductor $/MW slot at the sidecar plus compute-chassis boundary. SiC Schottky diodes and Si LV MOSFETs / IGBTs provide baseline content across cost-sensitive stages and battery switching. GaN participates via Layer 05 post-regulation on the compute tray. Sensors and MCUs are numerically many but per-unit small.

08The conversion boundary. Where value is captured

Two architectural options. Which boundary the sidecar implements determines which supplier layer captures the conversion value. Delta, LITEON and Chicony are examples on the sidecar side; Vicor, MPS, Navitas and EPC on the rack side.

Figure 8
The conversion boundary. Option A (HV direct) vs Option B (48V distribution)
OPTION A High-voltage DC to the compute rack Sidecar AC-DC only Layers 01-04, 06-10 ~800V 1 MW / ~800V ≈ 1.25 kA DC bus Busbar drop blind-mate feasible ~800V Compute rack Rack DC-DC (Layer 05) on tray / backplane ~800V → ~50V SiC + GaN Vicor, MPS, Navitas, EPC Trade-off: maximises sidecar standardisation, minimises heavy LV copper between racks. The high-ratio conversion problem moves into the compute vendor's scope. OPTION B Low-voltage distribution boundary Sidecar AC-DC + DC-DC step-down inside 48V 1 MW / 48V ≈ 20.8 kA DC bus 48V busbar difficult to scale 48V Compute rack Takes 48V directly Low-voltage rail delivered by sidecar Sidecar owns DC-DC Trade-off: keeps HV DC out of the compute chassis, but 20.8 kA between sidecar and rack makes the LV busbar physically difficult to scale. Blind-mate connector engineering constrains. P = V × I 1 MW / 800 V ≈ 1.25 kA   |   1 MW / 48 V ≈ 20.8 kA Investment framing. Every conversion stage that migrates from the sidecar into the compute rack changes where conversion value is captured, shifting scope between power-system vendors, power-shelf suppliers and rack-level DC/DC and semiconductor suppliers. LITEON participates on both sides today (480 VAC → 800 VDC power shelf and 800V DC/DC solutions), which is a preview of how vendor scope crosses this boundary.
At 1 MW, an 800V differential distribution path moves ~1.25 kA; the exact conductor current and sharing arrangement depend on whether the architecture is unipolar or bipolar (see §12). Option A puts the high-ratio conversion problem on the compute tray. Option B pushes DC-DC into the sidecar but exposes the sidecar-to-rack interface to 20.8 kA at 1 MW. The physics decides where the money goes.

09The 20 kA problem, to physical scale

1.25 kA vs 20.8 kA at 1 MW. What the copper looks like.

Figure 9
The busbar physics. 800V DC at 1.25 kA vs 48V DC at 20.8 kA, cross-sections to scale
OPTION A 800V DC busbar at 1.25 kA Copper busbar cross-section Drawn to scale relative to Option B ~10 x 5 mm (50 mm² area) 40 px = 10 mm METRICS Copper mass: ~0.4 kg per metre Blind-mate connector: standard OCP Diablo interface Rack-to-rack interconnect: feasible; commodity engineering Thermal budget at 1.25 kA: modest; forced air adequate OPTION B 48V DC busbar at 20.8 kA Copper busbar cross-section Drawn to same scale as Option A ~40 x 20 mm (or laminated stack, ~800 mm² area) ~16.7× the copper of Option A ~16.7× area of Option A METRICS Copper mass: ~7 kg per metre (~16.7× Option A) Blind-mate connector: bespoke; qualification is the hard part Rack-to-rack interconnect: physically constrained above ~500 kW Thermal budget at 20.8 kA: requires forced air or liquid cooling ∼16.7× more copper cross-section AND mass per metre Illustrative geometry. Actual busbar dimensions depend on current density (2.5-4 A/mm² typical), thermal management approach and IEC / UL clearance.
Moving from 48V distribution (20.8 kA at 1 MW) to 800V distribution (1.25 kA at 1 MW) reduces the current requirement by 16.7×. In a simplified current-density-limited conductor comparison, the required copper cross-section and copper mass per metre can fall by roughly the same factor. Actual busbar and cable design is additionally constrained by temperature rise, insulation, enclosure geometry, fault withstand, mechanical strength, creepage/clearance and installation configuration. That materially expands the practical design space for blind-mate connectors and rack-to-rack interconnects under Option A; Option B moves a much heavier current and conductor burden at the same delivered power.

10Why the sidecar exists

The sidecar survives only if the six pressures below outweigh the penalty of introducing another physical boundary between compute and power. The relative weight of each driver varies by deployment; several can reinforce the case for moving power outside the compute rack.

Figure 10
Six drivers behind the sidecar. Why power moves out of the compute rack
1 Reclaim rack space for silicon The rack is compute density. Every rack unit occupied by AC/DC + BBU is a rack unit not occupied by GPU. Relocating power to a sidecar frees the compute rack for accelerator density that the AI capex is buying. DRIVER TYPE · SILICON DENSITY 2 Solve the 20 kA problem at the rack boundary At 1 MW / 48V the rack-side busbar is 20.8 kA. Terminating AC-DC in a sidecar and dropping ~800V DC to the rack collapses the interface current to ~1.25 kA. Blind-mate connectors, busbar engineering and thermal budgets all shrink. DRIVER TYPE · CURRENT PHYSICS 3 Transient smoothing separated from ride-through GPU workloads swing tens of percent within milliseconds. The sidecar hosts a dedicated capacitor / supercapacitor bank for ms-scale smoothing, separated from the aluminum-capacitor energy storage that handles outage ride-through. DRIVER TYPE · DYNAMIC LOAD 4 Retrofit-friendly on existing 480 VAC feeds The sidecar takes 380-480 VAC 3-phase in. That is what existing switchboards deliver. No MV service upgrade, no new SST, no facility plant rework. The whole 800V DC delivery architecture terminates at the sidecar itself. DRIVER TYPE · BROWNFIELD PATH 5 Decouple power refresh from compute refresh Compute refreshes on 3-5 year cycles as GPU generations turn over. Power infrastructure has 8-12 year design life. Separating the two into distinct racks lets each refresh on its own cycle without stranding the other. DRIVER TYPE · ECONOMIC LIFECYCLE 6 Standardise the interface, not the compute rack OCP Diablo 400 defines the sidecar-to-rack interface (busbar drop, voltage, protection). Compute rack architectures can then evolve independently. Multi-vendor sidecar procurement against one interface spec becomes practical. DRIVER TYPE · INTERFACE STANDARD
The push-out drivers listed above cover silicon density on the rack, current physics at the rack boundary, dynamic load management, brownfield retrofit compatibility, economic lifecycle decoupling, and interface standardisation via OCP Diablo. Several can reinforce the case for moving power outside the compute rack; the relative weight varies by deployment.

11The transition timeline

Sidecar is the near-term hybrid architecture. The transition to facility-native 800V is happening on a rolling horizon.

Figure 11
Transition timeline. Legacy rack-integrated stack, sidecar today, native 800V facility
AUTHOR SCENARIO · DIRECTIONAL TIMELINE 2022 2024 2026 2027 2028 2029 2030 2031 2032 TODAY (2026) Legacy rack-integrated Dominant <2023 Long-tail legacy footprint Sidecar (this essay) SIDECAR VOLUME EXPANSION (SCENARIO) Delta 660 kW shipping Native 800V facility Rises 2028-2032 Hyperscaler-led Diablo 400 v0.5.2 Multi-topology 800V arrives Facility-native 800V at scale Sidecar becomes brownfield-only
Illustrative transition path, not a market forecast. Sidecar deployment expands as hybrid 800V architectures enter volume, while facility-native 800V architectures develop in parallel as SST and associated protection ecosystems mature. AUTHOR SCENARIO: sidecar volume could concentrate in the late 2020s before facility-native architectures take a larger share; the exact rollover stays unestablished.

12What changes with native 800V

"800V" is used throughout this piece as the nominal architecture class; the OCP LVDC documents specify several lower nominal distribution configurations within that class, including 350/700V bipolar and 700V unipolar variants. Grounding, protection and device class differ across each.

Figure 12
Native 800V spans several architectures. Five OCP LVDC configurations, five delta profiles
350/700V bipolar TN-S w/ midpoint 350/700V bipolar TN-S w/o midpoint 350/700V bipolar IT (no midpoint) 700V unipolar TN-S 700V unipolar IT Grounding topology Distributed midpoint TN-S Split TN-S, no midpoint IT (isolated) Grounded return TN-S IT (isolated) Midpoint monitoring / protection Required N/A per topology N/A per topology N/A per topology N/A per topology GFD / IMD requirement GFD at midpoint Per-rail GFD IMD required Return-path GFD IMD required SiC device relevance 1200V-class increasingly relevant 1200V-class increasingly relevant 1200V-class increasingly relevant 1200V-class becomes primary path 1200V-class becomes primary path Rectifier topology impact Retains balanced half-bridges Simplified balanced stages Isolated stack topology Fewer half-bridge stages Fewer, isolated stages Connector requalification Rated at rail voltage Rated at rail voltage IT-suitable insulation 700V continuous rating 700V continuous + IT insulation Arc + fault protection Requirements scale with continuous voltage + fault energy; architecture varies with the selected 700/800V topology THE FRAMING CORRECTION The next architecture moves past "±400 becomes +800." The 800V ecosystem contains multiple grounding and conductor configurations, with bipolar 350/700V and unipolar 700V implementations each carrying different protection, insulation and interface implications. The principal current reduction comes from moving to an ~800V differential distribution. The further change from bipolar ±400V to unipolar ~800V changes grounding, conductor and protection architecture rather than automatically halving delivered current. SiC voltage ratings migrate upward; 1200V-class devices become increasingly relevant to the 700/800V path.
Five OCP LVDC configurations, each with distinct grounding, protection and connector implications. Only architectures with a distributed midpoint retain a midpoint-related monitoring/protection requirement. IT variants use insulation monitoring as part of the protection architecture; grounded-midpoint fault-detection arrangements sit elsewhere. Rectifier topology simplifies at unipolar; SiC voltage class migrates upward.
SO WHAT FOR UNDERWRITERS

Sidecar vendor: ask which of the five topologies the vendor supports today. Multi-topology support reduces dependence on any single architecture; single-topology exposure is a more concentrated architectural bet.

SiC device vendor: verify 1200V-class MOSFET and Schottky product roadmap plus fab capacity. Wolfspeed, onsemi, STMicro and Infineon each run different mixes.

Connector / busbar vendor: ask about 700V continuous requalification status. IT-topology insulation qualification is a separate workstream.

Hyperscaler infrastructure plan: ask which topology the hyperscaler's published architecture and procurement programme align with. Google, Microsoft and NVIDIA are actively collaborating through OCP on the 800V architecture and MVAC-to-800V workstream.

13Who captures the value

Three stacks. Conversion arrows that disappear destroy a market; arrows that remain concentrate value into whoever owns them.

Figure 13
Where conversion value migrates across legacy, sidecar and native 800V stacks
STACK 1 · PAST The legacy rack-integrated stack 480 VAC AC/DC on rack Legacy PSU array ~48/54V distribution Chassis distribution GPU / accelerator VENDOR CAPTURE In-chassis PSU vendors Board-level DC/DC STACK 2 · TODAY The sidecar stack 480 VAC Sidecar AC/DC Layer 02, SiC-heavy ~800V DC / ±400V bus Sidecar to rack busbar drop Rack DC/DC Layer 05, chassis-resident GPU / accelerator VENDOR CAPTURE Sidecar AC/DC: Delta, LITEON, Chicony Rack DC/DC: Vicor, MPS, Navitas, EPC STACK 3 · TOMORROW The native 800V facility stack MV AC SST / MV AC to 800V DC At facility level 800V DC distribution Row-level or hall-level busbar Rack DC/DC Chassis-resident, ~800V direct GPU / accelerator VENDOR CAPTURE Facility SST: new merchant market Rack DC/DC: concentrates further WHAT DISAPPEARS In-chassis PSU array (displaced by sidecar). Sidecar AC/DC layer (displaced by native 800V facility). ~48/54V distribution (partly reshaped). Each transition removes or reshapes a conversion market. WHAT REMAINS AND CONCENTRATES Rack DC/DC (survives all three stacks; concentrates further into fewer high-ratio stages). Facility SST is a new conversion market that native 800V creates. Every arrow that remains is where value concentrates. So the question is which vendor holds the layers that persist.
Three stacks side by side. Legacy: rack-integrated AC/DC + ~48/54V distribution. Sidecar today: 480 VAC to sidecar AC/DC to ~800V DC bus to rack DC/DC to GPU. Native 800V tomorrow: MV AC to facility SST to 800V distribution to rack DC/DC to GPU. Each transition removes or resets a conversion market and concentrates value in the stages that remain.

14The vendor field

Sidecar vendors map on two axes: native-sidecar vs extending from an adjacent category, and merchant vs hyperscaler-integrated.

Figure 14
Sidecar vendor field. Native vs extended, merchant vs hyperscaler-integrated
MERCHANT + NATIVE SIDECAR MERCHANT + EXTENDED HYPERSCALER + NATIVE HYPERSCALER + EXTENDED Delta 660 kW in-row shipping; multi-topology portfolio (SST, DC/DC shelf, EVA) LITEON Dual-scope: 480 VAC → 800 VDC shelf AND 800V DC/DC solutions Chicony Power-shelf integrator Flex Sidecar integration Vertiv UPS + PDU heritage extending into sidecar / power-shelf products Advanced Energy Semiconductor power heritage extending into data centre AC/DC Bel Power PSU heritage; 800V shelves Schneider Electric Facility electrical + rack PDU Meta / Google / Microsoft internal OCP Diablo 400 co-authors; internal reference architectures ahead of merchant NVIDIA reference GB200 / Vera Rubin power reference designs shape merchant sidecar procurement Hyperscaler + Vertiv/Delta Joint-development programmes on hybrid designs (announced partnerships from 2025-2026) Semiconductor foundational Wolfspeed, onsemi, STMicro, Infineon via NVIDIA 800V ecosystem programmes ← NATIVE SIDECAR PRODUCT LINE EXTENDED FROM ADJACENT CATEGORY → ↑ MERCHANT HYPERSCALER-INTEGRATED ↓ READING THE MAP Illustrative vendor field. Positioning reflects publicly disclosed product scope and current programme participation, not market share. Hyperscaler-integrated designs (Meta, Google, Microsoft, NVIDIA references) sit below the line and drive merchant procurement above it.
Illustrative sidecar vendor field on two axes. Positioning reflects publicly disclosed product scope and current programme participation, not market share. Vendor classifications ("800V product", "sidecar-form", "OCP participation") should be verified against each vendor's current specification and shipping status before use in diligence; product announcements, reference designs and shipping commercial products are distinct categories. Hyperscaler internal programmes set the specification that merchant vendors deliver against.

15What could kill the sidecar

The sidecar depends on two conditions holding: native-800V facility SST arriving slower than sidecar deployment, and rack thermodynamics staying air-plus-DTC; mass-immersion sits elsewhere. If either changes materially, the sidecar's addressable role could shrink or its form factor could need to change (see Q3 for the redesign case).

Figure 15
Risk quadrant. What could displace the sidecar architecture
← LOW IMMERSION PENETRATION HIGH IMMERSION PENETRATION → ← SLOW NATIVE 800V ARRIVAL FAST NATIVE 800V ARRIVAL → TOP-LEFT · CURRENT THESIS PATH Sidecar remains important Native 800V arrives on the slower path (2029-2032). DTC + sidecar remains the deployed architecture for the brownfield stock. Delta / LITEON / Chicony and rack DC/DC merchants share the value pool. Sidecar relevance: 5+ years of peak volume SIDECAR RELEVANCE: HIGH HIGH TOP-RIGHT · ACCELERATED 800V Sidecar bypassed by facility SST Hyperscalers pull facility-native 800V forward, MV AC-to-800V SST reaches volume 2027-2028. New greenfield deployments skip the sidecar layer. Sidecar retreats to brownfield-only retrofit. Sidecar relevance: brownfield-only, declining volume SIDECAR RELEVANCE: MEDIUM-LOW MED-LOW BOTTOM-LEFT · IMMERSION MAINSTREAM Sidecar constrained by rack thermodynamics Immersion cooling breaks the DTC + sidecar architecture assumption. Compute rack physical layout rethought around immersion tanks. Sidecar interface + form factor need redesign. SIDECAR RELEVANCE: MEDIUM (redesigned) MED BOTTOM-RIGHT · BOTH DRIVERS FLIP Sidecar irrelevant fast Facility-native 800V AND mainstream immersion arrive together. Compute rack + facility architecture skip the sidecar layer entirely. Investment in sidecar vendor scope becomes brownfield-terminal. SIDECAR RELEVANCE: LOW LOW
Four scenarios on two axes. Top-left is the current thesis path where the sidecar remains important. Top-right compresses sidecar volume as facility-native 800V arrives. Bottom-left forces sidecar redesign around immersion form factors. Bottom-right eliminates the sidecar layer entirely. The quadrant mix determines which parts of the sidecar vendor's technology stack remain valuable.
OBSERVABLE DILIGENCE TESTS FOR SIDECAR-VENDOR UNDERWRITING

Watch: hyperscaler facility-SST procurement. Meta, Google, Microsoft or other hyperscaler tenders for MV-AC-to-800V facility SST at production volume are the leading signal for Q2/Q4 arriving faster than the base case. Contract awards, not press releases.

Watch: immersion deployment at >100 kW rack-equivalent density. Two-phase or single-phase immersion moving into production AI infrastructure at scale is the leading signal for Q3/Q4. Distinguish demonstration deployments from committed capex.

Vendor durability check. Ask whether the sidecar vendor's technology stack survives the top-right and bottom-left scenarios. Native-topology-agnostic AC/DC content survives top-right; immersion-compatible mechanical design survives bottom-left. Single-topology exposure is a more concentrated architectural bet.

16Topology per risk scenario

Each Fig 15 quadrant has a distinct physical topology. Power path, cooling, grounding, and 10-layer BOM impact for each.

Q1 · Sidecar remains important. Slow 800V + low immersion

The current thesis path. 480 VAC in from grey-space, sidecar rack does the AC-DC + BBU + DC bus, ~800V DC drops into the compute rack, on-tray DC-DC to GPU. Cooling stays DTC. All ten sidecar BOM layers are active.

Figure 16a
Q1 detailed topology. Sidecar remains important · full 10-layer BOM active
Q1 · SLOW 800V + LOW IMMERSION Sidecar remains important. Full 10-layer BOM applies to the sidecar rack. POWER PATH · 480 VAC → SIDECAR → ±400 VDC / 800 VDC → COMPUTE FACILITY LV Grey-space switchboard 480 VAC 3-phase 400A MCCB EMI/EMC filter SPD Class II ABB / Eaton / Schneider 3-ph AC SIDECAR RACK · 660 kW REFERENCE (DELTA) S6 6 × 18.5 kW AC/DC PSU 80 kW BBU (Al-cap ES) Cap bank (ms) 110 kW S5 6 × 18.5 kW AC/DC PSU 80 kW BBU (Al-cap ES) Cap bank 110 kW S4 6 × 18.5 kW AC/DC PSU 80 kW BBU (Al-cap ES) Cap bank 110 kW S3 6 × 18.5 kW AC/DC PSU 80 kW BBU (Al-cap ES) Cap bank 110 kW S2 6 × 18.5 kW AC/DC PSU 80 kW BBU (Al-cap ES) Cap bank 110 kW S1 6 × 18.5 kW AC/DC PSU 80 kW BBU (Al-cap ES) Cap bank 110 kW Total: 660 kW output · 480 kW BBU · 36 × 18.5 kW PSUs Bus: ±400 VDC bipolar · midpoint TN-S grounding Protection: Bender GFD at midpoint + IMD Diablo 400 v0.5.2 · SiC: Wolfspeed / onsemi / STMicro / Infineon ±400 VDC BUSBAR DROP OCP Diablo blind-mate 1.25 kA line current at 1 MW differential load Amphenol / Anderson Molex / TE / Harting ±400 VDC COMPUTE RACK · VERTICAL AIR-DTC Layer 05 · Rack DC-DC (compute-chassis) 1RU 90 kW 800V → 50V (Delta) OR on-tray DC-DC Vicor / MPS / Navitas / EPC (high-ratio SiC + GaN) GPU tray · ~50V → on-die POL → 0.7-1.1V @ die GPU tray · cold plates on ASIC + HBM GPU tray · ~100 kW class Rack density: 100+ kW · rack form: vertical air-DTC Blind-mate: 800V DC + fluid QDs on cold plate manifold NVIDIA GB200 / Vera Rubin class COOLING PATH · DTC LIQUID + FACILITY CDU + AIR RESIDUAL Facility water plant Chilled water 20-45°C Cooling towers or dry cool Existing brownfield plant Untouched by AI retrofit CDU (L2L) Row-level ~2.4 MW Heat exchanger + pump Delta EVA / CoolIT-Ecolab Motivair / Boyd Row manifold Supply + return Blind-mate QDs Leak detection cable Sensata / TE / nVent Cold plate on GPU 2500-3500 W/socket ASIC + HBM coverage CoolIT / Boyd / Motivair Fluid: PG25 or PG40 Residual air (CRAH / fanwall) Handles PSU + rack loss + PDU Sidecar itself is air-cooled (Diablo 400) Vertiv / Stulz / Schneider CRAH Existing hall infrastructure 10-LAYER BOM IMPACT · ALL LAYERS ACTIVE IN THIS SCENARIO LAYER STATUS DETAIL IN Q1 01. Input + protection ACTIVE 480 VAC 3-ph, 400A MCCB, EMI filter, SPD Class II (MOV/TVS/GDT) 02. AC-DC conversion ACTIVE · PRIMARY 36 × 18.5 kW AC/DC PSUs across 6 shelves (Delta / LITEON / Chicony) 03. DC bus structure ACTIVE ±400 VDC bipolar with distributed midpoint TN-S (Diablo 400 v0.5.2) 04. Energy storage ACTIVE 6 × 80 kW BBU (Al-cap ES) = 480 kW total + per-shelf cap banks (ms smoothing) 05. DC-DC intermediate ACTIVE · compute chassis Rack DC-DC (Delta 1RU 90 kW OR on-tray Vicor / MPS / Navitas / EPC) 06. Protection + monitoring ACTIVE Bender GFD at midpoint + IMD; Hall sensors (LEM / Allegro); AFDD MCU 07. Controls + comms ACTIVE PLC + BACnet/Modbus to site EPMS; TI/ADI/Renesas/ST MCUs on shelves 08. Busbar drop ACTIVE OCP Diablo blind-mate connector; 1.25 kA line current at 1 MW (Amphenol / Anderson / Molex / TE) 09. Thermal management ACTIVE · air-cooled Diablo 400: air-cooled (fan drivers Si); Sanyo Denki fans; sidecar dissipation via room air 10. Cabinet + physical ACTIVE OCP 21" enclosure, EMC shielding, seismic bracing (Rittal / nVent / Chatsworth)
Full Q1 topology. Facility 480 VAC → 660 kW sidecar rack (6 × 110 kW shelves, each 6 × 18.5 kW AC/DC PSUs + 80 kW BBU with aluminum-capacitor energy storage) → ±400 VDC bipolar bus at midpoint TN-S → OCP Diablo blind-mate busbar drop (1.25 kA at 1 MW across the 800 V differential) → compute rack with 90 kW rack DC-DC → GPU trays. DTC cooling via row CDU and cold plates; sidecar itself air-cooled per Diablo 400. All ten functional layers are represented in the overall architecture; Layer 05 remains in the compute chassis; sidecar placement falls away.

Q2 · Sidecar bypassed by facility SST. Fast 800V + low immersion

Facility SST arrives fast. MV AC to 800V DC at facility level; row-level busway to compute rack. Sidecar disappears from the physical path. Layers 02/04/06 migrate to facility scope; the rest eliminate at the sidecar.

Figure 16b
Q2 detailed topology. Sidecar bypassed · layers migrate to facility SST
Q2 · FAST 800V + LOW IMMERSION Sidecar bypassed. Facility SST + hall busway take over; sidecar 10-layer BOM migrates or is eliminated. POWER PATH · MV AC → FACILITY SST → 800V DC HALL BUSWAY → COMPUTE FACILITY MV Utility feed or on-site MV 11-33 kV AC MV switchgear SF6 / vacuum breaker MV surge protection Utility + ABB / Hitachi MV AC FACILITY SST · MULTI-MW (ILLUSTRATIVE STACK) Stage 1 · MV rectifier + input filter SiC 1700V or 3.3kV MOSFETs; input EMI + fault-current limiter Stage 2 · HF isolation transformer Medium-frequency (5-20 kHz); nanocrystalline or ferrite core Stage 3 · 800V DC rectifier + output filter SiC 1200V MOSFETs + Schottky; output capacitor bank; CT + ADC Stage 4 · Protection + facility BESS interface DC AFDD, GFD/IMD, ride-through interface to facility BESS (min-hr) Multi-MW class (2-10 MW/unit) · single-conversion architecture Output: 800V DC unipolar (LVDC TN-S or IT variants) Delta SST / ABB / Hitachi Energy / EPC Power SiC devices: Wolfspeed 1700V/3.3kV; onsemi; Infineon; STMicro 800V DC 800V HALL BUSWAY Row/hall-level DC distribution Rated: ~800V continuous Segmented DC MCCB GFD at row segments Starline / Legrand / Delta 800V DC COMPUTE RACK · VERTICAL AIR-DTC (unchanged from Q1) Layer 05 · Rack DC-DC (compute-chassis) 1RU 90 kW 800V → 50V (Delta) OR on-tray DC-DC Vicor / MPS / Navitas / EPC unchanged GPU tray · ~50V → on-die POL GPU tray · cold plates on ASIC + HBM GPU tray · ~100 kW class Rack density: 100+ kW · rack form: vertical air-DTC Blind-mate: 800V DC direct (no sidecar intermediate) NVIDIA GB200 / Vera Rubin class (unchanged from Q1) COOLING PATH · DTC LIQUID + FACILITY CDU (unchanged from Q1) Facility water plant + row CDU Chilled water 20-45°C, ~2.4 MW L2L CDU Delta EVA / CoolIT-Ecolab / Motivair / Boyd Thermal architecture preserved — power path changed only Row manifold + cold plate DTC Blind-mate QDs, leak detection cable 2500-3500 W/socket cold plates (CoolIT / Boyd) Unchanged from Q1 WHAT CHANGED · POWER ONLY The DTC cooling stack does not change in Q2. Only the power path is rearchitected. Sidecar functions (AC-DC + BBU + DC bus) migrate to the facility SST. Ride-through migrates to facility BESS. 10-LAYER BOM IMPACT · SIDECAR LAYERS MIGRATE OR ARE ELIMINATED LAYER STATUS WHERE IT GOES IN Q2 01. Input + protection ELIMINATED at sidecar Facility MV switchgear replaces 480 VAC LV input entirely 02. AC-DC conversion MIGRATES to facility SST vendor SiC content migrates to facility SST scope (Delta / ABB / Hitachi Energy / EPC Power) 03. DC bus structure ELIMINATED at sidecar Sidecar-internal DC bus gone; replaced by facility 800V hall busway (Starline / Legrand) 04. Energy storage MIGRATES to facility BESS Battery ride-through moves upstream to facility BESS (minutes-hours); shelf BBU eliminated 05. DC-DC intermediate ACTIVE · compute chassis (unchanged) Rack DC-DC (Vicor / MPS / Navitas / EPC) unchanged — still needed to reach 50V 06. Protection + monitoring MIGRATES to facility scope GFD/IMD/AFDD move to facility SST + busway segments (Bender / Littelfuse / Eaton) 07. Controls + comms ELIMINATED at sidecar Facility EPMS handles all monitoring; sidecar-local PLC/BMS not needed 08. Busbar drop ELIMINATED at sidecar No sidecar-to-rack drop; compute rack taps facility busway directly 09. Thermal management ELIMINATED at sidecar No sidecar rack means no sidecar thermal budget; facility SST thermal is separate scope 10. Cabinet + physical ELIMINATED at sidecar Sidecar cabinet footprint gone; facility SST housing is separate infrastructure category
Full Q2 topology. Facility MV AC feed → multi-MW facility SST (illustrative stack: MV rectification → HF isolation → 800V conversion → protection/BESS interface) → 800V DC hall busway → compute rack (unchanged Layer 05 DC-DC → GPU trays). Cooling stack unchanged from Q1. Sidecar-level BOM: Layer 02 migrates to facility SST, Layer 04 migrates to facility BESS, Layer 06 migrates to facility protection scope, Layer 05 unchanged. Remaining layers are eliminated from the sidecar BOM (they remain at the system level, picked up elsewhere).

Q3 · Sidecar redesigned for immersion. Slow 800V + high immersion

Native 800V slow; immersion mainstream. Sidecar retained but Layers 08, 09, 10 redesigned. Compute moves from conventional liquid-cooled rack infrastructure into an immersion-qualified enclosure or tank architecture.

Figure 16c
Q3 detailed topology. Sidecar retained but redesigned · compute in immersion tanks
Q3 · SLOW 800V + HIGH IMMERSION Sidecar retained but Layers 08, 09, 10 redesigned for an immersion-qualified enclosure. POWER PATH · 480 VAC → SIDECAR (REDESIGNED) → 800V DC → IMMERSION TANK FACILITY LV Grey-space switchboard 480 VAC 3-phase 400A MCCB EMI/EMC filter SPD Class II Unchanged from Q1 3-ph AC SIDECAR RACK · REDESIGNED FOR IMMERSION-TANK INTERFACE Layers 01-07 · unchanged AC-DC + BBU + DC bus + protection + controls (as Q1) Layer 08 · Busbar drop: REDESIGNED New connector: 800V DC + dielectric-fluid-tolerant seal ring; tank penetration through immersion vessel wall; new blind-mate class. Layer 09 · Thermal: REDESIGNED Sidecar itself may share the immersion-hall thermal loop; liquid coldplates on SiC MOSFETs plausible at high shelf density. Layer 10 · Cabinet: REDESIGNED Vessel-adjacent form factor; sealed penetrations; safety-certified for hall. Rittal / nVent / Chatsworth redesign programme. Output: ~800V DC (unipolar or bipolar per site topology) Interface + form factor change is the key architectural risk ~800V DC TANK INTERFACE Sealed 800V tank penetration Dielectric-fluid seal Vapour-tight if 2-phase Custom OCP variant? Amphenol / Molex new class ~800V DC IMMERSION TANK · HORIZONTAL DIELECTRIC VESSEL Submerged DC-DC (Layer 05 adapted) Immersion-compatible modules; conformal coating; dielectric-fluid rated Vicor / MPS / Navitas / EPC (immersion-qualified) Compute blades submerged in dielectric fluid GPU + memory + on-tray DC-DC + POL ~100 kW per blade class Two-phase (3M Novec) OR single-phase (mineral / synthetic HC) Vendors: Submer / GRC / LiquidStack / Iceotope / Asperitas Horizontal vessel replaces vertical compute rack entirely COOLING PATH · TWO-PHASE OR SINGLE-PHASE IMMERSION → FACILITY HEAT REJECTION Immersion tank fluid loop Dielectric fluid boils at chip (~50-60°C, 2-phase) or circulates at ~25-40°C (single-phase) Vapour condenses at tank lid HX No CDU intermediate Facility heat rejection Dry cooler (ambient) or chiller Higher supply temp than DTC enables free cooling more of the year Higher-efficiency thermal profile FLUID CHEMISTRY RISK Dielectric fluid chemistry drives BOM 3M Novec end-of-life triggered a global search for replacement 2-phase fluids. PFAS regulatory pressure accelerates single-phase HC adoption. See DTC cooling essay + leak-detection stack. 10-LAYER BOM IMPACT · SIDECAR LAYERS 08/09/10 REDESIGNED LAYER STATUS CHANGE IN Q3 01. Input + protection UNCHANGED 480 VAC input identical to Q1 02. AC-DC conversion UNCHANGED AC/DC PSU stack unchanged from Q1 03. DC bus structure UNCHANGED Diablo 400 bus topology retained 04. Energy storage UNCHANGED BBU + capacitor stack unchanged 05. DC-DC intermediate REDESIGNED (immersion-compatible) On-tray DC-DC now submerged; conformal coating + fluid-rated packaging 06. Protection + monitoring UNCHANGED GFD/IMD topology retained (bipolar or unipolar per site) 07. Controls + comms UNCHANGED EPMS handoff identical; adds tank sensors 08. Busbar drop REDESIGNED (tank penetration) New connector class: sealed dielectric-fluid-tolerant tank penetration 09. Thermal management REDESIGNED (liquid or hall-shared) Sidecar itself may be liquid-cooled or share immersion-hall thermal loop 10. Cabinet + physical REDESIGNED (form factor) New enclosure adjacent to tank; sealed penetrations; hall safety qualification
Full Q3 topology. Sidecar rack retained. Layers 01-07 remain broadly in scope, while Layers 08-10 are the most visibly redesigned: Layer 08 (busbar drop) requires an immersion-compatible electrical interface, Layer 09 (thermal) may migrate into the immersion heat-rejection system, Layer 10 (cabinet) changes with the enclosure form factor. Compute moves from conventional liquid-cooled infrastructure into an immersion-qualified enclosure or tank architecture; on-tray DC-DC (Layer 05) requires immersion-qualified variants. Cooling may shift to an immersion-based heat-rejection architecture, potentially eliminating or materially changing the CDU function depending on the specific implementation.

Q4 · Sidecar eliminated. Fast 800V + high immersion

Both drivers flip. Facility SST + immersion-qualified compute enclosure replace the sidecar path in this scenario. Ride-through migrates to facility BESS; DC-DC migrates to immersion-qualified on-tray modules.

Figure 16d
Q4 detailed topology. Sidecar eliminated · facility SST + immersion-qualified enclosure replace the sidecar path
Q4 · FAST 800V + HIGH IMMERSION Sidecar eliminated. Facility SST + immersion tanks displace both the sidecar rack and the vertical compute rack. POWER PATH · MV AC → FACILITY SST → 800V DC HALL → IMMERSION TANK (direct) FACILITY MV Utility feed or on-site MV 11-33 kV AC MV switchgear SF6 / vacuum breaker Same as Q2 MV AC FACILITY SST · MULTI-MW (ILLUSTRATIVE STACK, same as Q2) Stage 1 · MV rectifier SiC 1700V or 3.3kV; input EMI Stage 2 · HF isolation transformer Nanocrystalline core, 5-20 kHz Stage 3 · 800V DC rectifier + output filter SiC 1200V MOSFETs + Schottky Stage 4 · Protection + facility BESS DC AFDD, GFD/IMD, ride-through to facility BESS Multi-MW class (2-10 MW/unit) Output: 800V DC unipolar Delta SST / ABB / Hitachi Energy / EPC Power 800V DC 800V HALL BUSWAY Row/hall-level DC distribution Segmented DC MCCB GFD at row segments Direct tap to tank Starline / Legrand / Delta 800V DC IMMERSION TANK · DIRECT 800V FEED (no sidecar intermediate) Submerged DC-DC (Layer 05 adapted) On-tray 800V → 50V; conformal coating; dielectric-rated Vicor / MPS / Navitas / EPC (immersion-qualified) Compute blades submerged in dielectric fluid GPU + memory + on-tray DC-DC + POL ~100 kW per blade class Facility 800V DC lands directly on the tank penetration No sidecar rack, no vertical compute rack. CDU function may be reset or removed. Submer / GRC / LiquidStack / Iceotope + on-tray Vicor / MPS COOLING PATH · FACILITY-SCALE IMMERSION → DRY COOLER / CHILLER (CDU role reset) Immersion tank fluid Two-phase (dielectric refrigerant) OR single-phase mineral / synthetic HC Boils at chip; condenses at lid HX Facility heat rejection Dry cooler / chiller / cooling tower Higher supply temp = more free cooling Facility-scale, CDU role reset END-STATE ARCHITECTURE Power and cooling both facility-native. Sidecar as a category may cease to exist. The conventional vertical rack may cease to be the dominant physical form. The dark case for sidecar-vendor equity. 10-LAYER BOM IMPACT · SIDECAR LAYERS DISPLACED IN FULL LAYER STATUS WHERE IT GOES IN Q4 01. Input + protection ELIMINATED at sidecar MV switchgear replaces LV input entirely 02. AC-DC conversion MIGRATES to facility SST vendor Facility SST captures Layer 02 SiC content (Delta / ABB / Hitachi Energy / EPC Power) 03. DC bus structure ELIMINATED at sidecar Facility 800V hall busway replaces sidecar DC bus (Starline / Legrand) 04. Energy storage MIGRATES to facility BESS Battery ride-through moves upstream to facility BESS; shelf BBU eliminated 05. DC-DC intermediate REDESIGNED (immersion-qualified) On-tray DC-DC submerged; Vicor / MPS / Navitas / EPC immersion variants 06. Protection + monitoring MIGRATES to facility scope Facility SST + busway include GFD/IMD/AFDD (Bender / Littelfuse / Eaton) 07. Controls + comms ELIMINATED at sidecar Facility EPMS + tank-level BMS handle all monitoring 08. Busbar drop ELIMINATED at sidecar Tank penetration functions as a facility-to-tank interface; the sidecar-to-rack drop no longer exists 09. Thermal management ELIMINATED at sidecar No sidecar means no sidecar thermal; SST thermal is separate scope 10. Cabinet + physical ELIMINATED at sidecar Sidecar cabinet gone; SST housing is a separate infrastructure category
Full Q4 topology. Facility MV AC → multi-MW facility SST (unchanged from Q2) → 800V DC hall busway → immersion-qualified compute enclosure directly (no sidecar intermediate). Immersion can change the thermal interface and may reset or remove the conventional rack CDU depending on the heat-rejection architecture; higher supply temperature enables more free-cooling hours. Sidecar 10-layer BOM: Layers 02, 04, 06 migrate to facility SST/BESS/protection; Layer 05 redesigned for immersion; Layers 01, 03, 07, 08, 09, 10 are eliminated from the sidecar BOM (they remain at the system level, picked up elsewhere). The conventional vertical rack may cease to be the dominant physical form.
WHAT CHANGES BETWEEN QUADRANTS

Power path: Q1 uses 480 VAC + sidecar AC/DC. Q2 and Q4 use MV AC + facility SST. Q3 keeps 480 VAC + sidecar AC/DC but with a redesigned tank interface.

Rack form: Q1 and Q2 use vertical compute racks. Q3 and Q4 use immersion-qualified compute enclosures; the physical form factor may differ from the conventional vertical rack.

Cooling architecture: Q1 and Q2 use DTC liquid + facility CDU. Q3 and Q4 use immersion (two-phase or single-phase) with dielectric fluid connecting to facility heat rejection; the CDU role may be reset or removed depending on the specific implementation.

Sidecar role: Q1 all 10 layers active. Q2 mostly eliminated, Layers 02/04/06 migrate to facility. Q3 all layers present, Layers 05/08/09/10 redesigned. Q4 all layers displaced. Sidecar-vendor durability tracks how many quadrants the vendor's product survives.

Method + sources. Anchor references from Delta Americas (660 kW / 6×110 kW shelf / 80 kW BBU per shelf / 18.5 kW AC/DC PSUs / 1RU 90 kW 800V→50V DC/DC shelf), Open Compute Project (Diablo 400 v0.5.2 ±400V midpoint architecture; DCF Power Distribution LVDC white paper covering 350/700V bipolar TN-S with and without distributed midpoint, IT variants, and 700V unipolar TN-S / IT), and NVIDIA 800 VDC architecture material. Vendor examples across LITEON, Chicony, Flex, Vertiv, Vicor, MPS, Navitas, EPC, Wolfspeed, onsemi, STMicro, Infineon, Bender, LEM, Allegro, TI, ADI, Renesas.

BOM value definition. "BOM value" throughout this piece means estimated equipment-level hardware value at the sidecar boundary, before installation, engineering, integrator margin and site costs. It excludes manufactured BOM, component cost, installed equipment cost and supplier revenue. BOM allocation ranges in Figure 4 and the sensitivity in Figure 5 are AUTHOR SCENARIO illustrative estimates. Supplier quotations and disclosed product BOMs are outside the source set. BBU baseline is ~60-90 seconds ride-through (author scenario, not an OCP or Delta specification) and should be verified against product-specific implementation before use. Layer 05 is excluded from the total to prevent double-counting with compute-tray DC/DC. Transition timeline in Figure 11 is directional; adoption pace depends on hyperscaler procurement volume, SST maturity, and immersion cooling deployment.

No advisory relationship with any named party. Nothing here is investment advice.