> ## Content Index > Fetch the complete content index at: https://adikumar.co/llms.txt > Use this file to discover other available public pages before exploring further. # The On-Package Delivery Stack: Technical Companion - URL: https://adikumar.co/the-on-package-delivery-stack-technical-companion/ - Published: 2026-08-02T01:35:47.000Z - Updated: 2026-10-07T05:39:11.000Z - Description: IVR magnetics, thin-film substrates, high-density capacitors and the qualification-gated architecture of on-package power delivery. - Author: Adi Kumar - Tags: #Essay, AI Power Chain, Semiconductors, Power electronics, Technical [The AI Power Chain series](https://adikumar.co/ai-power-chain/) · Part 10 of 15 Technical Companion · Part V # The On-Package Delivery Stack: circuit design, physics, process A deeper walk through IR drop budgeting, multi-phase current sharing, backside power etch flows, and the design tooling that keeps an 0.8V rail stable across 2,250 amperes and thousands of transient domains. Update · post-close Analog Devices completed the acquisition of Empower Semiconductor on 7 July 2026 for approximately $1.5B. References to Empower below describe the business and technology now inside ADI. The market-position and merchant-competition framing throughout the piece reflects Empower's standalone posture through mid-2026, before close. Companion to the **The On-Package Delivery Stack** essay (Part V of six). Use this piece for the circuit design, process integration and reliability arguments; use the main essay for the market map, TAM and profit-pool thesis. ## Section 1: The IR drop budget, from first principles The tightest number in AI silicon design is the transistor supply voltage tolerance. On a 3nm process, a nominal 0.75V core rail typically has a tolerance window of ±5% of nominal, or ±37.5mV. That number has to cover four independent effects: DC IR drop across the power delivery network, AC ringing on step-load transients, process variation of the transistor threshold, and thermal drift over the operating temperature range. The DC IR budget that the power delivery network is allowed to consume is therefore not ±37.5mV. It is closer to **±15-20mV** after the other three effects have taken their slices. Now do the resistance math. If an accelerator draws 1,800W at 0.8V, that is 2,250A of DC current. Holding IR drop below 15mV at 2,250A requires the total DC path resistance from the board-level VRM output to the transistor gate to be: R\_total < 15 mV / 2,250 A = 6.67 µΩ Six and two-thirds micro-ohms across a path that spans centimetres of substrate copper, millimetres of interposer routing, tens of micrometres of on-die metal stack, and a stack of TSVs and micro-bumps in between. The individual budget components look like this on a typical modern design: Where the 15mV IR budget goes: a representative accelerator Per-segment IR drop, illustrative, mV at 2,250A total current, front-side vs backside delivery Author's illustrative decomposition. Segments are: motherboard traces from VRM to package pins; package substrate + solder bumps; interposer TSVs; on-die metal stack (M0 through top-metal power grid); local via stack down to transistor. The BSPDN variant reallocates the on-die burden away from the front-side metal stack. Two observations from that decomposition. First, no single segment dominates the budget; the design is a distributed optimisation problem. Second, the segment that scales worst with current is the on-die metal stack, because its resistance is set by the transistor node's minimum metal pitch, which shrinks as node scales, driving resistance up quadratically at the smallest lines. This is the physics that pushes the industry toward backside power delivery: BSPDN moves the highest-current segments off the tightly-pitched front-side metal and onto a separately-fabricated back-side stack that can be routed with much wider, thicker metal. ### Why R matters more than L on a DC rail (and vice versa on transient) Power delivery network analysis operates in two regimes. In steady state, the network is a distributed resistor and R alone determines DC IR drop. On transient (a step-load event where the processor's current consumption changes by hundreds of amperes within a nanosecond), the network is a distributed R-L-C, and the impedance seen by the load includes the reactive terms. A modern accelerator PDN targets a flat impedance profile from DC up to several hundred megahertz, and every violation of that profile shows up as voltage ringing at the transistor. Z\_PDN(f) target: < 500 µΩ across DC → 200 MHz for a 0.8V, 2,250A rail Meeting 500 µΩ impedance flatness from DC through 200MHz requires a hierarchical decoupling capacitor architecture. Bulk aluminium electrolytic capacitors at the VRM output handle DC through 10kHz. Ceramic capacitors on the motherboard handle 10kHz through 1MHz. Package-mounted MLCCs handle 1MHz through 30MHz. On-package deep-trench capacitors (integrated into the substrate or the interposer) handle 30MHz through 300MHz. And on-die MOS-capacitor arrays handle 300MHz and above. Each capacitor class has to be sized and placed so that its impedance region overlaps its neighbour with no resonant peak between them. Getting this wrong is the second most common cause of transistor throttling on new accelerator silicon, behind thermal throttling. A modern accelerator PDN targets a flat impedance profile from DC up to several hundred megahertz. Every violation of that profile shows up as voltage ringing at the transistor, and every millivolt of ringing shows up as a lower attainable clock frequency.The design constraint that governs everything else In brief Vertical vs lateral point-of-load, on-chip capacitor physics and package tolerances drive how efficiently 48V or 800V becomes 0.8V at the GPU die. IR-drop budgets under 3mV per phase drive vertical-power adoption. Package inductance and pad density constrain converter placement. Physics + geometry + thermal budget together determine which topology wins at a given power density. ## Section 2: Multi-phase current sharing and the physics of 20 interleaved buck converters The workhorse converter that steps 48V or 12V down to 0.8V at the accelerator's core rail is a multi-phase interleaved buck converter. The topology is the same as the buck converter in any laptop charger, replicated N times and phase-offset by 360°/N. If eight phases share a 2,250A load, each phase moves roughly 280A. Each phase also switches at a different point in the switching cycle, so the ripple at the output capacitor cancels between phases, reducing the required output capacitance by roughly a factor of N. Interleaved multi-phase output ripple Illustrative output current ripple range, one phase vs eight phases interleaved, same total load Author's illustration of interleaved multi-phase ripple cancellation. Peak-to-peak ripple falls approximately linearly with phase count for well-matched phases. Ripple cancellation is imperfect at any real phase count because component tolerances (inductor value, MOSFET R\_DS(on), switching timing) prevent perfect cancellation; typical measured cancellation ratio is 60-75% of ideal. The two hard engineering problems in multi-phase design are *current sharing* and *transient response*Current sharing is the requirement that all N phases move equal fractions of the load current in steady state, so that no single phase runs hotter than its neighbours. Because component values vary between phases (inductor inductance ±5%, MOSFET R\_DS(on) ±10%), passive current balancing does not work at high phase counts. Modern controllers therefore implement **active current balancing**: they measure the current in each phase individually (using either an on-die sense resistor, an inductor DCR-based estimation, or a magnetic pickup on the output inductor) and adjust each phase's on-time to equalise currents. The DrMOS parts that Monolithic Power, Infineon and Renesas sell are packaged with the current-sense circuitry built into the same silicon as the power switches, which is what makes them qualify as "AI-grade" versus lower-grade multi-phase modules that rely on external sense components. Transient response is the requirement that when the accelerator's current draw suddenly changes (a compute workload starts or stops), the converter's output voltage stays within its tolerance window. The response speed is set by the converter's control loop bandwidth, which is bounded above by the switching frequency (typically 500kHz to 2MHz for a multi-phase POL). Higher switching frequency = faster transient response = lower required output capacitance, but also = higher switching loss = lower efficiency. Modern multi-phase controllers use **digital hysteretic control** or **constant on-time control** to push transient response toward the theoretical single-switching-cycle limit, at the cost of more complex control loop design and higher susceptibility to noise coupling. ### Coupled inductors: the modern optimisation A recent design refinement is the **coupled inductor** multi-phase topology. Instead of each phase having its own independent inductor, a group of phases (typically 2 or 4) share a magnetically-coupled multi-winding inductor. The coupling adds two useful properties: it lets the inductor operate at a lower effective inductance during transients (fast response) while presenting a higher effective inductance in steady state (low ripple), and it reduces the total magnetic volume by roughly 30-40% versus discrete inductors of the same rating. Coupled inductor multi-phase controllers are now standard on AI accelerator VRM designs and are one of the differentiating features of the MPS MP288x family and the Infineon TDA family. ## Section 3: The magnetics problem in on-package IVR The main essay explained why on-package IVR is attractive: shorter current loop, higher switching frequency, smaller passive components, less IR drop. The reason the magnetic component is the hard part is worth spelling out. The output inductor in a buck converter stores energy during the switch's on-time and releases it during the off-time. The size of the inductor is set by the required inductance value and the peak current it must handle without saturating the magnetic core. Inductance is proportional to the number of turns squared and to the core's permeability, so higher permeability core material = smaller inductor for the same inductance. But high-permeability materials saturate at low flux density, which limits the peak current the inductor can handle. There is an unavoidable tradeoff between inductance density and current capacity. Energy stored = ½ × L × I² · Volume required ∝ Energy / (B\_sat² / µ\_r) The design lever that makes on-package IVR work is switching at very high frequency (20-100MHz), which reduces the required inductance by the same factor and therefore reduces the required magnetic volume by the same factor. But at those frequencies, conventional soft-magnetic materials (ferrites, powdered iron) have unacceptable core losses because their magnetic domain walls cannot follow the applied field fast enough, dissipating energy as heat. On-package IVR requires **thin-film magnetic materials** accordingly: sputtered iron-cobalt or nickel-iron alloys deposited in layers separated by insulating films, with each layer thin enough (typically <100nm) that the magnetic domains can respond to megahertz-scale fields with acceptable loss. Core loss vs frequency: bulk vs thin-film magnetics Representative core loss density (mW/cm³) at \~50mT flux excursion, for common bulk cores vs thin-film IVR stacks Author's compilation from vendor datasheets (Ferroxcube, Magnetics, TDK) and IEEE PELS conference papers on thin-film magnetics (2020-2025). Loss numbers vary substantially with material composition, lamination thickness and flux excursion; the chart shows an illustrative case at 50°C, 50mT peak-to-peak. Thin-film magnetics are the technology moat that Empower and Ferric (now TDK) built. The specific process recipes (alloy composition, layer thickness, annealing profile, insulation material) are trade secrets protected by decade-long development programs. There is no commodity supply of thin-film IVR magnetics; a would-be entrant has to develop their own process from scratch and validate it against a design partner's requirements, a two-to-three-year exercise even with existing semiconductor process capability. The IVR market has consolidated to two vendors on exactly that basis, and Chinese entry is absent for the same reason. ## Section 4: BSPDN process flow, in enough detail to matter Backside Power Delivery Networks run as a family of process integrations that share the same top-level idea; a single-process framing understates the variants (put a metal power stack on the back of the die) but differ substantially in how they get there. The two dominant flows are **buried power rails** (Intel PowerVia) and **backside via + backside metal** (TSMC SuperPower Rail). Both flows begin the same way, with a conventional front-side process producing the transistor plane and the front-side metal stack up to some intermediate layer. The divergence starts after front-side processing is complete. ### Intel PowerVia flow (18A) PowerVia's distinguishing feature is **buried power rails**: dedicated power interconnect routed at the M0 layer *underneath* the transistor plane, contacted through the transistor's source and drain via nano-TSVs that penetrate the substrate. The sequence: 1. Front-side wafer processing produces the transistor plane with the buried power rails already in place at M0. 2. Front-side metal stack is built up in the conventional way, but without the top-metal power distribution grid. 3. Wafer is flipped and temporarily bonded to a carrier wafer for backside processing. 4. Bulk silicon is thinned from \~800µm down to \~5µm using grind-then-CMP. 5. Backside vias are etched down to the buried power rails at M0. 6. Backside metal stack is deposited: two or three thick metal layers (typically 4-10µm each of copper) that form the backside power distribution grid. 7. Backside solder bumps are formed, temporary carrier is released, wafer is diced. The advantages: the buried power rails are already integrated with the transistor at M0 so the on-die power grid path is extremely short. The trade-off: the buried power rails have to be placed during front-side processing, before the transistor layout is complete, so the process integration is deeply coupled to the standard cell library design. Intel's 18A cell library was redesigned specifically to support PowerVia, and much of the \~2 year gap between announcement and volume production went into that library redesign. ### TSMC SuperPower Rail flow (N2P and A16) SuperPower Rail's distinguishing feature is **backside via to source/drain contact**: instead of routing power at M0 and contacting the transistor from below, TSMC routes the front-side metal as usual (including M0) and etches backside vias that contact the transistor's source and drain directly from the back. The sequence: 1. Front-side wafer processing produces the transistor plane and the conventional M0 through top-metal front-side stack. 2. Wafer is flipped and temporarily bonded to a carrier wafer. 3. Bulk silicon is thinned to \~5µm. 4. Backside vias are etched down to the transistor's source/drain contacts. This is a more challenging etch than PowerVia's because it requires stopping precisely on \~10nm-thick contact regions, but avoids the front-side library redesign. 5. Backside metal stack is deposited (typically 2-3 layers, thick copper). 6. Backside bumps, carrier release, dicing. The advantages: the front-side cell library does not need to be redesigned, so it inherits the existing N2 library. The trade-off: the backside via etch is technically harder than PowerVia's, requiring novel etch chemistries and inline metrology to hit the source/drain landing pad with sub-nanometre alignment. TSMC's N2P timeline reflects the additional process development effort. BSPDN process integration: PowerVia vs SuperPower Rail vs Samsung BSPDN Illustrative comparison of process step count, thermal budget and integration complexity Author's compilation from IEDM 2024/2025 papers (Intel 18A, TSMC N2/A16, Samsung SF2P), plus IMEC technical reports on BSPDN process variants. Values are illustrative (not measured); the actual process metrics are commercially sensitive. **Yield ramp is where the money hides.** The public disclosures on both PowerVia and SuperPower Rail describe the process as "yielding". They do not disclose the yield curve. Industry consensus is that BSPDN adds roughly 4-6 percentage points of yield loss versus the equivalent front-side-only process during the first six to nine months of production, and closes to \~1 point of yield loss by month twelve. On a $20,000-per-wafer leading-edge node, four points of yield loss on a 500-die wafer is roughly $80 per die of extra cost, which is the largest single reason why BSPDN-equipped accelerators are priced at a premium during their first-year sales window. ## Section 5: Glass substrate process integration Glass substrates enter datacenter packaging at the interposer-below layer, replacing organic ABF laminate. The key process step is drilling through-glass vias (TGVs) at the required aspect ratio and density. There are three commercial approaches: **Laser ablation.** A picosecond or femtosecond laser drills each via individually. This is fast for low via counts but scales linearly with via count, which becomes a bottleneck at datacenter packaging densities (10,000+ TGVs per package). **Plasma etch.** A photolithographic mask is patterned on the glass surface and reactive-ion etching cuts the vias in parallel. Higher throughput but more capital-intensive, and requires specialised plasma chemistries for glass. **Modified glass with photoactive additives.** The glass sheet contains photosensitive dopants that, when exposed to UV, become preferentially etchable in an acid bath. This is the Corning approach, and it produces the highest via density (up to \~30,000 vias/cm²) with the lowest per-via cost, at the trade-off of being tied to Corning's proprietary glass composition. Absolics (SKC's US subsidiary) uses a variant of the plasma etch approach adapted from Korean display-industry equipment, which is why the Absolics facility is in the US southeast (adjacent to display substrate suppliers); South Korea proper hosts a different line. Intel's in-house glass substrate line uses proprietary equipment developed internally over roughly a decade, with volume ramp targeted for 2027. Through-glass via approaches Illustrative comparison of throughput, achievable via density, and equipment capex Author's compilation from ECTC 2024/2025 papers on glass substrate processing, Absolics/SKC investor presentations (2025), and Corning IP disclosures. Values are directional; process capabilities are competitively sensitive. ## Section 6: Reliability failure modes at the transistor-scale power path The main essay treated the on-package power stack as an engineering problem. The reliability side is worth its own section because the failure modes are novel to the AI generation of accelerators. ### Electromigration at 2nm Electromigration is the movement of atoms within a conductor under the momentum transfer of flowing electrons. At high current density, electromigration hollows out one end of a conductor and piles atoms up at the other, eventually opening the conductor. The failure rate scales exponentially with current density and with temperature. Conventional copper interconnect at 5nm nodes tolerates current densities of \~2 MA/cm² at 105°C for a 10-year lifetime; at 3nm, the tolerable density drops to \~1.2 MA/cm² because the interconnect cross-section shrinks faster than the current requirement. The industry responses: (a) replace copper with cobalt or ruthenium at the smallest metal layers (Ru has 2-3x better electromigration resistance than Cu at the same dimensions), (b) redistribute current across more parallel paths using BSPDN, (c) implement per-domain current limiting in the microarchitecture to cap the peak current density in any single wire, and (d) accept a shorter design lifetime (5-year, down from 10-year) for the current-conducting-density-critical wires. All four are visible on Rubin-generation silicon. ### EMIB and hybrid bonding stress cycles Advanced packaging introduces multiple new interfaces where materials with different coefficients of thermal expansion meet. Every thermal cycle stresses those interfaces. The most vulnerable interfaces on a Blackwell or Rubin package are the die-to-interposer solder bumps and the interposer-to-substrate solder bumps. Historical thermal cycling tests use military-standard 55°C swings, which falls short of representative for AI accelerator use where the die can swing from 40°C idle to 105°C load in under a second and cycle that swing thousands of times per training run. Reliability qualification labs are updating their test protocols to include these fast thermal cycles, and initial data suggests the historical qualification standards were 2-3x optimistic on lifetime for AI-workload thermal profiles. **The reliability question that has not been answered yet.** BSPDN-equipped accelerators are less than two years into field deployment on Intel 18A, less than one year on TSMC N2P. Field data stays limited to distinguish "backside processes are more reliable" from "backside processes are less reliable" over a 5-10 year operating window. Historical qualification tests suggest they are equivalent to front-side processes, but historical tests do not capture the full thermal-cycling profile of AI workloads. This is the largest single unknown in the reliability story of the current accelerator generation. ## Section 7: PDN simulation and design tooling Getting a modern AI accelerator's power delivery network right is a co-design problem that spans the transistor layout, the on-die metal stack, the interposer, the substrate, the multi-phase controller, the board-level power tree, and the CDU delivery upstream. No single tool can simulate the whole path at the fidelity required. The industry uses a hierarchy of tools: **Transistor-level SPICE simulation** for the innermost 1-10mm of the path, capturing individual gate switching events, per-cell current draws and local IR drop. **Extracted-parasitic PDN simulation** for the on-die metal stack through the top-metal power grid, using 3D field solvers (Ansys HFSS, Cadence Clarity, Synopsys HSPICE-Signoff) to extract resistance and inductance per grid segment, then AC-analysing the network in the frequency domain. **Package + board co-simulation** for the substrate through the VRM output, typically in Ansys SIwave or Cadence Sigrity, with S-parameter models of the multi-phase controller and DrMOS parts stitched in. **System-level VRM control loop simulation** for the VRM through the delivery point, in PSIM or Simplis, with the load modelled as a step-current source and the entire regulation loop closed. No commercial tool exists that stitches all four levels together into a single time-domain simulation. The industry standard workflow is to run each tool independently, exchange S-parameters and impedance profiles at the tool boundaries, and iterate until a consistent solution emerges. This iteration is where roughly 20-30% of the pre-silicon design schedule of a modern AI accelerator is spent, and it is the largest single reason why AI accelerator design cycles have lengthened from 18 months to 30 months over the last three generations. Any tooling vendor that can shorten this loop has an enormous market to sell into. ## Section 8: What a design review of a new accelerator's power delivery would ask To close, here is the checklist that a chief silicon architect might apply when a new hyperscaler AI accelerator design lands on their desk. It is it captures the questions that separate a competent design from a competitive one. | Layer | The question | What "good" looks like on Rubin-generation silicon | | -------------------- | ----------------------------------- | --------------------------------------------------------------------------------------- | | Transistor supply | Nominal V\_core and IR budget? | 0.65-0.85V nominal, ±15mV DC IR budget, ±25mV total tolerance window | | On-die PDN | Peak local current density? | < 1.2 MA/cm² on the highest-density metal layers using Cu; < 2.5 MA/cm² on Ru layers | | BSPDN? | Front-side only, or BSPDN? | BSPDN on any accelerator above \~1,500W total power for the leading-edge tier | | Interposer | CoWoS variant and TSV density? | CoWoS-L or -S, ≥10,000 total TSVs, ≥30% dedicated to power | | Substrate | Organic ABF or glass? | Glass on flagship tier from 2027; ABF elsewhere | | IVR | Merchant IVR, foundry IVR, or none? | Merchant IVR from Empower or TDK on flagship tier; foundry-integrated on 2028+ designs | | Multi-phase POL | Phase count, coupled inductors? | ≥12 phases per rail; coupled inductors on flagship tier; MPS or Infineon reference part | | Decoupling hierarchy | PDN impedance flatness? | < 500 µΩ from DC through 200MHz; hierarchical bulk/ceramic/on-package/on-die caps | | Thermal coupling | Junction temperature at max power? | < 105°C junction on cold plate; matched to Part III cold plate microchannel spec | | Transient response | Voltage droop on step load? | < 8% droop on 500A/ns step; recovery within 3 switching cycles | A modern AI accelerator's power delivery network is ten stacked ones, from transistor cell library through backside process choice through interposer variant through IVR selection through multi-phase phase count. Each layer's decision constrains the layer above and below. Miss any of them and the accelerator either does not clock at spec or throttles under sustained load.The design review, in one paragraph Related topic hubs - [AI Power Semiconductors](https://adikumar.co/ai-power-semiconductors/) - [800V Data Centre Power](https://adikumar.co/800v-data-centre-power/) - [Browse all topic hubs →](https://adikumar.co/topics/) ### Annex · References Intel PowerVia disclosures: IEDM 2023 paper on 18A process integration; Intel Foundry Direct Connect 2024 investor day materials. TSMC SuperPower Rail: IEDM 2024 papers on N2 backside power delivery integration; TSMC 2025 technology symposium. Samsung Foundry BSPDN roadmap: Samsung Foundry Forum 2024 disclosures; IEDM 2025 papers on SF2P. imec technical publications on BSPDN process variants (2022-2025). Ferric Semiconductor (now TDK) thin-film IVR magnetics: IEEE APEC 2023-2024 papers. Empower Semiconductor product briefs, 2024-2025 releases. Corning glass substrate technical disclosures: ECTC 2024, IPC APEX 2025. Absolics (SKC) investor commentary on Covington GA facility ramp, 2025-Q3 and Q4. MPS multi-phase controller architecture: MP288x family datasheets and evaluation guide. Ansys, Cadence and Synopsys product documentation on PDN sign-off flows. ### Companion to main essay Read alongside the main essay "The On-Package Delivery Stack" (Part V of six) for the market map, TAM and profit-pool arguments. This companion focuses on the engineering physics; the main essay focuses on the vendor and margin structure.